Method and apparatus for low cost signature testing for analog and RF circuits

Abstract

A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

Description

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a method and apparatus for low cost signature testing for testing analog and RF circuits. More particularly, the invention relates to such a method and apparatus for use in manufacturing testing, and for use in monitoring the manufacturing process.

[0003] Analog and RF circuits are characterized by a set of performance parameters that typically vary continuously over a range. These performance parameters result from design as modified by variations in the manufacturing process that occur over time. Because of this variation, it is often necessary to test at least some of the circuits produced by a given manufacturing process to ensure that the performance parameters of the circuits fall within given specification limits.

[0004] However, traditional testing methods impose an increasing burden in the form of test time as a result of the ever increasing complexity and speeds of analog and RF circuits. For example, straightforward testing employs automated or automatic test equipment (“ATE”) to stimulate the circuit under test (CUT) in a manner designed to induce the circuit to provide an output which directly reflects the value of each performance parameter which it is desired to test. The output is used to determine whether the parameter is within specification limits, in which case the CUT is considered “good” or is considered to “pass,” or whether the parameter is outside the specification limits, wherein the CUT is considered “bad” or is considered to “fail.” Each performance parameter requires, in general, a specific stimulus appropriate for testing that parameter and a corresponding output measurement, and it is therefore time consuming to step through all of the required test stimuli to obtain the performance parameters of interest in this manner.

[0005] Various techniques have been proposed to minimize this test time and, therefore, the cost of testing. Such techniques have attempted to arrive at a single test stimulus effective for discerning whether the CUT passes or fails. For example, S. J. Tsai, “Test vector generation for linear analog devices,” International Test Conference, pp. 592-597, 1991, characterizes the circuit as either “good” or “bad” as a result of its response to a stimulus that maximizes the difference in response between circuits having these characterizations. The stimulus is obtained by optimization methods, wherein the impulse responses for good and bad circuits are used as input to an optimization model, the result of which produces the test stimulus.

[0006] Alternatively, as in W. Lindermeir, H. E. Graeb and K. J. Antreich, “Design of Robust Test Criteria in Analog Testing,” International Conference on Computer Aided Design, pp. 604-611, 1995, a user provides a set of proposed test stimuli, and the method provides for choosing the one that is most effective at discriminating between “good” and “bad” circuits.

[0007] Some serious drawbacks of these methods are that neither is applicable to non-linear circuits, and neither provides quantitative information about the circuit performance parameters themselves. Further the method of the latter reference places a demand on the user to provide a set of test stimuli, hence the method provides no assistance in generating or optimizing the test stimuli.

[0008] Moreover, an additional problem encountered in testing RF circuits is the need for very high frequencies in the test signal. This imposes an additional cost on testing, as the ATE needed to produce high frequency test signals of arbitrary shape is more complex and difficult to use. Neither of the aforementioned prior art test methodologies has addressed this problem.

[0009] Accordingly, there is a need for a method and apparatus for low cost signature testing of both RF and analog circuits that provides more information about circuit performance parameters and provides more information about the manufacturing process.

SUMMARY OF THE INVENTION

[0010] The method and apparatus for low cost signature testing for analog and RF circuits according to the present invention solves the aforementioned problems and meets the aforementioned needs by providing a model adapted to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus.

[0011] The optimized test stimulus is applied to manufactured circuits under test for testing the quality of the circuits, and output signatures are obtained. The output signatures thereby obtained are preferably applied to a non-linear model to obtain more accurately predicted performance parameters for the manufactured circuits.

[0012] Therefore, it is a principal object of the present invention to provide a novel and improved method and apparatus for low cost signature testing for analog and RF circuits.

[0013] It is another object of the invention to provide such a novel and improved method and apparatus for low cost signature testing for analog and RF circuits that efficiently reduces test time and therefore cost.

[0014] It is yet another object of the invention to provide such a novel and improved method and apparatus that provides for maximizing prediction accuracy.

[0015] It is still another object of the present invention to provide such a method and apparatus for low cost signature testing for analog and RF circuits that provides more information about circuit performance parameters than would otherwise be available.

[0016] It is a further object of the present invention to provide such a method and apparatus for low cost signature testing for analog and RF circuits that provides for calibrating for short or long term variations in the manufacturing process.

[0017] The foregoing and other objects, features and advantages of the present invention will be more readily understood upon consideration of the following detailed description of the invention, taken in conjunction with the following drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 is a flow chart of a preferred method for developing an optimized test signal as part of a method for low cost signature testing of electronic circuits according to the present invention.

[0019] FIG. 2 is a preferred form of a test stimulus according to the present invention.

[0020] FIG. 3 is a flow chart illustrating construction of a non-linear model according to the present invention.

[0021] FIG. 4 is a flow chart of a preferred method for manufacturing testing according to the present invention using the optimized test stimulus of FIG. 1.

[0022] FIG. 5 is a flow chart for an autocalibration method according to the present invention.

[0023] FIG. 6 is a flow chart of a preferred method for low cost signature testing of RF electric circuits according to the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0024] The present application incorporates herein by reference in its entirety the publication by inventors R. Voorakaranam and A. Chatterjee entitled “Test Generation for Accurate Prediction of Analog Specifications,” IEEE VLSI Test Symposium, pp. 137-142, 2000. This publication provides mathematical explanation, background and support for methods according to the invention that are described herein in a simplified manner. Also incorporated herein is the inventor's paper, submitted to the International Test Conference 2001, entitled “Low-Cost Signature Testing of RF Circuits,” attached hereto as Appendix A.

[0025] With reference to FIG. 1, a flow chart of a preferred method for low cost signature testing 100 of electronic circuits is shown. Each of the circuits has a set of performance parameters P(I), I=1 . . . L, that must fall within a range bounded by a corresponding set of performance specifications. If one or more of the parameters falls outside of the corresponding specification for the parameter, the circuit fails the test; otherwise, the circuit passes. However, it is an outstanding feature of the present invention that the method and apparatus provide an estimate of the performance parameters as well as indicating whether or not the performance parameters meets their specifications without directly testing them. The typical context for the method 100 is that there are a number of the electronic circuits “C” obtained from a common manufacturing process for the circuits. The manufacturing process may be characterized by process parameters “Proc(g)”, g=1 . . . G, that will vary about mean values of the process parameters over time. The process parameters form a G-dimensional “process parameter space.”

[0026] In a step 101, the process parameters Proc(g) are perturbed, one at a time, by a small amount, so that, preferably, there is one perturbed value “Pert(g)” for each process parameter. Correspondingly, in a step 102 of the preferred method 100, one circuit “C(g)” is produced under the process conditions represented by each perturbed value Pert(g).

[0027] Turning to step 103, traditional ATE testing is conducted on the circuits “C(g)”, i.e., C(1), C(2), . . . C(G), and the circuits' performance parameters “Pg(i)”, i.e., P1(i), P2(i), . . . PG(I), are obtained in Step 106. For example, one of the performance parameters Pg(i=1) may be the slew rate for the circuit C(g), and another performance parameter Pg(i=2) may be the gain of the circuit C(g) at a particular frequency. The performance parameters of the circuits measured or otherwise obtained in the traditional manner are referred to herein as “actual” performance parameters Pg(i)A. In step 107, “g” is iterated in steps 101-106.

[0028] In another step 108 of the preferred method, which may be conducted at any time relative to steps 102 to 106, a test stimulus Stim(k) (k=0, 1, . . . k) is selected. Initially, where k=0, the test stimulus is selected arbitrarily in anticipation of later, iterative optimization. Preferably, for simplifying the methodology, the test stimulus is selected to be a piece-wise linear function of time having a relatively small number of breakpoints, such as five to ten breakpoints BP (see FIG. 2).

[0029] The stimulus Stim(k) is physically applied to the circuit C(1) (Step 110), and the circuit's response is measured over time (Step 112). Preferably, the circuit's response to the stimulus is sampled at predetermined regular time intervals Δt to provide a set of samples forming a “signature” Sig(g, k, t) for the circuit C(g) corresponding to the stimulus Stim(k) at a predetermined time sample t.

[0030] In step 113, “g” is iterated in steps 110 and 112, i.e., these steps are carried out with respect to circuits C(2), C(3), . . . C(G). Accordingly, by the conclusion of step 113 for the initial stimulus Stim(k=0), each of the circuits C(g) has been stimulated with the stimulus Stim(0), corresponding signatures Sig(g,O,t) have been determined, and corresponding actual performance parameters P1(i)A, P2(i)A, . . . PG(IiA have been measured.

[0031] In steps 114a and 114b, the measured signatures and performance parameters for all of the circuits C(g), i.e., Σg Sig(g, k, t), and Σg Pg(i)A, are provided to a step 115 wherein a linear predictive model LPM(k) is constructed for the present stimulus Stim(k). The linear predictive model is used for predicting performance parameters, wherein “predict” as used herein is synonymous with “estimate” and is not intended to signify foretelling of future events.

[0032] The linear predictive model relates the measured signatures Σg Sig(g,k,t) to the measured performance parameters Σg Pg(i)A, by a set of simultaneous, linear equations. For example, for the stimulus Stim(0), the linear model LPM(0) is a matrix of coefficients representing the solution of simultaneous linear equations relating the measured signatures Sig(g, 0, t) to the measured performance parameters Pg(i)A.

[0033] Turning to steps 116-118, the LPM(k) is used to receive as an input the signatures Sig(g, k, t) and to produce as an output a prediction or estimate of the performance parameters of the circuit Pg(i, k)p, assuming that the signatures Sig(g,k,t) result from stimulating the circuit C(g) with the stimulus Stim(k). In step 120, the predicted performance parameters are compared with the actual performance parameters obtained from step 114b and an error “e(k)” is obtained (Step 122) that is representative of the prediction error for the set of circuits C(g).

[0034] It may be noted that there would be no prediction error in predicting the measured performance parameters Pg(i,k)A for the circuits C(g) from the signatures actually used to obtain the measured performance parameters if the model perfectly mapped measured signatures to measured performance parameters. However, the linear model assumes linear relationships between the performance parameters and the signatures where these relationships are generally non-linear. Notwithstanding, the error introduced by using a linear model is minimized according to the invention by use of a less costly procedure than would be required for constructing a more accurate, non-linear model.

[0035] In practice, each performance parameter will have associated therewith a component of the prediction error, and a total error to be minimized may be defined as the mean squared error summed equally over all of the performance parameters, or the performance parameters may be weighted if desired to emphasize the relative importance of selected parameters. The error may further be defined in other ways as desired without departing from the principles of the invention.

[0036] The inventors have recognized that the prediction error “e(k)” depends on the test signal and can be minimized by determining a test signal that is optimum for this purpose. Moreover, by optimizing the test signal to minimize this error, the test signal is made robust in terms of the capability to induce circuits under test, whose performance parameters are subject to further process variations, to produce signatures from which those performance parameters can be predicted.

[0037] According to the invention, the prediction error “e(k)” is minimized by iteratively varying the test stimulus Stim(k). Any standard iterative optimization method may be employed for this purpose. The test stimulus Stim(k) is varied by choosing new breakpoints or adding or deleting segments, and repeating steps 103-118 (Step 126) until the error “e(k)” falls within an acceptable maximum ξ. This provides an optimized test stimulus Stim(k)optimized and a linear predictive model LPM(k)optimized that may be used with the optimized test stimulus for use in manufacturing test as discussed below in connection with FIG. 3.

[0038] Because the linear predictive models LPM(k) consider only small linearized variations in the process parameters, the error “e(k)” is due to linearization errors introduced by the linear model (σ2 (mdl)) and measurement noise variance (σ2 (nse)). A preferred objective or cost function for minimizing the total error “e(k)”=(σ2 (tot)=σ2 (mdl)+σ2 (nse)) is:

F=Σk j , (for j=1 . . . n),

[0039] where:

k j =1+[(1−(σ(tot)/ξ]/n for σ (tot)<ξ,

[0040] or

k j =σ(tot)ξ for σ (tot)≧ξ,

[0041] where “n” is the number of circuits sampled. The objective function is preferably minimized as a result of using a genetic algorithm for optimizing the piece-wise linear test stimulus.

[0042] As is apparent from FIG. 1, revised linear predictive models are preferably constructed for each iteration of the test stimulus. The number of predictive models that are constructed in this iterative process suggests the advantage of using linear models as opposed to non-linear models to optimize the test stimulus. The present inventors have recognized that the test signal optimized using iterative linear models is adequate for testing purposes and the method is significantly less costly than obtaining a non-linear model having greater predictive accuracy, especially where the non-linear model employs an iteratively optimized test stimulus.

[0043] All of the aforementioned steps are taken in advance of actual manufacturing testing, where an investment in time may be made without impacting the manufacturing process. For actual manufacturing test, a non-linear predictive model “NLPM” is preferably constructed for use with the optimized test signal Stim(k)optimized found by use of the iteratively determined linear predictive models of steps. A preferred method for constructing the NLPM is provided by J. H. Friedman, “Multivariate Adaptive Regression Splines,” The Annals of Statistics, Vol. 19, No. 11-141, incorporated by reference herein in its entirety. However, other known mathematical methods may be employed for constructing the NLPM as desired without departing from the principles of the invention. Referring to FIG. 3, similar to the LPM, the NLPM is constructed to relate measured signature outputs Sig(g,t) from several manufactured “training” circuits (“trng Cg”), as opposed to simulation models. The training circuits are stimulated with Stim(k)optimized, and measured performance parameters Pg(i)A for the training circuits are obtained.

[0044] Turning to FIG. 4 wherein a manufacturing test process 400 is illustrated, once the optimized test stimulus and NLPM are found and determined, they may be employed in a manufacturing test strategy by applying the optimized test stimulus Stim(k)optimized to any number of manufactured circuits under test (“mfd.CUT”) (Step 402), sampling the outputs of the circuits to obtain signatures therefor (Step 404), applying the signatures to the NLPM (Step 406), and obtaining predicted performance parameters for each of the circuits (Step 408) at the output of the NLPM. In this way, a significant time saving is realized for each test, since a single test stimulus produces an accurate prediction of performance parameters for the circuits.

[0045] The manufacturing process used to produce the electronic circuits will shift or drift over time as well as fluctuate differently (either more or less) than at the time of carrying out the construction of the non-linear model NLPM. In other words, the NLPM may not characterize the process adequately as the process changes over time. To detect and correct for this circumstance, a method 500 shown in FIG. 5 according to the present invention is preferably used to “autocalibrate” the NLPM. In a preferred form of the method, the signature responses for each manufactured circuit under test (step 502) are obtained from step 404 (FIG. 4) and statistically analyzed (step 504). For example, the mean, maximum and minimum value of the signatures for the manufactured devices may be noted. These statistical parameters may be compared to the same kind of parametric data recorded for the training circuits to determine a deviation (step 506). This may be done for each manufactured circuit individually or, preferably, the information obtained from a number of the manufactured circuits may be pooled, the number being chosen to provide a statistically significant inference that the deviation reflects a significant process change. Such a circuit or set of circuits provides one or more “outlier circuits.”

[0046] Where the deviation in one or more of the parameters for such outlier circuits is determined to have reached a predetermined threshold level (step 508), the NLPM is preferably updated to reflect the additional information provided by the outlier circuits. More particularly, the signature outputs of the outlier circuits are obtained and performance parameters for the outlier circuits are measured (Step 509). An “updated” NLPM is constructed (Step 510) using the outlier circuits as additional data points. More particularly, where the original or previous NLPM is constructed based on a set of training circuits g=G1, the updated NLPM may be similarly constructed based on the set of training circuits g=G1+the number of outlier circuits, where the outlier circuits are reflective of the changed process. Alternatively, an entirely new NLPM could be constructed by obtaining additional “new” or “updated” training circuits.

[0047] Turning to FIG. 6, a method 600 that is particularly adapted for testing RF circuits according to the invention is illustrated. In the method 600, step 110 of the method 100 (see FIG. 1) is modified by modulating an RF carrier with the stimulus Stim(k). The modulated RF carrier is applied to the circuit C(g), and its response is measured over time as in step 112. Additional steps 612 and 614 are provided wherein the response is demodulated by the RF carrier and low-pass filtered. A device interface board DIB is provided for modulating the carrier with the test stimuli, demodulating the signature outputs of the circuits under test, and passing the demodulated outputs through a low pass filter LPF.

[0048] The modulation/demodulation scheme employed in the method 600 is arbitrary, it being understood that any modulation/demodulation scheme may be employed without departing from the principles of the invention.

[0049] Steps according to the present invention that apply an input to one of the models, or obtain an output of the models, may be accomplished in a computer at the instruction of a computer program, which may be embodied in any machine-readable form, such as encoded in volatile or non-volatile semiconductor memory or floppy disk. The models themselves are preferably computerized models, meaning for purposes herein that the models are accessible for use by a computer. Where actual electrical stimuli are applied to actual circuits, or where actual outputs from the actual circuits are obtained, any testing equipment or device known in the art for carrying out these actions may be employed.

[0050] It is to be recognized that, while a particular low cost signature test for RF and analog circuits has been shown and described as preferred, other configurations and methods could be utilized, in addition to those already mentioned, without departing from the principles of the invention.

[0051] The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention of the use of such terms and expressions of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.

Appendix A

Low-Cost Signature Testing of RF Circuits

Ram Voorakaranam and Abhijit Chatterjee Ardext Technologies Inc., Atlanta, Ga.

[0052] Abstract: Production test costs for today's RF circuits are rapidly escalating. Two factors are primarily responsible for this cost escalation: (a) The high cost of RF ATE and (b) Long test times demanded by elaborate performance tests. In this paper, we propose a low-cost test approach for the test of RF circuits using modulation of a low frequency test signal and subsequent demodulation of the DUT response. The demodulated response of the DUT is used as a signature from which all the performance specifications are predicted. We believe the proposed low-cost solution can be easily built into a load board that can be inter-faced to an inexpensive tester.

[0053] 1.0 Introduction

[0054] With the explosion in the wireless industry, RF integrated circuits are being used increasingly in a wide range of applications. Manufacturers of wireless applications are integrating RF, analog and digital blocks on the same silicon die for better performance and low cost. Production testing of high performance RF circuits is a major component of total RF electronics manufacturing cost because of elaborate tests and expensive testers. New RF test solutions are needed to keep pace with the phenomenal growth in the wire-less industry, and the ever increasing consumer demand for products with higher functionality at low price.

[0055] Signature testing has been proposed as a low cost alternative to specification testing of analog circuits [1,2]. It has been shown that without explicitly testing for the circuit specifications, analog performance can be predicted by using the transient response of the DUT as a signature (hence the name signature test). This technique coupled with a systematic test optimization procedure enables robust testing while reducing test costs dramatically.

[0056] The use of modulated signals for the test of RF circuits has been well studied in the past [3]. Recently, a new technique called Modulated vector network analysis (MVNA) [4] has been proposed for making classic RF measurements on wideband modulated signals. Using modulated signals, the technique is capable of measuring S-parameters and performing signal analysis using a single data acquisition. Further, this technique allows the behavior of the wideband components to be tested close to their real-world operation.

[0057] In this paper, we propose a new signature testing approach [5] for testing RF circuits using test signal modulation and test response demodulation. The proposed approach involves the following steps:

[0058] 1. The ATE supplies carefully designed baseband test stimulus to the loadboard.

[0059] 2. On the load board, the test stimulus is modulated onto a carrier. This modulated carrier is the test input signal to the DUT.

[0060] 3. DUT response is demodulated and baseband signal is sent back to the ATE.

[0061] 4. The design of the test stimulus (baseband+carrier) is done in such a way that performance variations in DUT cause significant changes in the response seen by the ATE. The emphasis of the proposed approach is to provide a highly cost-effective solution for production testing of RF circuits. The attractive features of our solution are (a) The modulator and demodulator can be easily built into the DUT loadboard and (b) The test signal applied to the loadboard and the signature response to be measured are both baseband, facilitating the use of a low cost ATE.

[0062] The rest of the paper is organized as follows. Section 2 describes the proposed approach for RF signature test and a procedure for test signal optimization. Section 3 discusses application of the proposed approach to the testing of a low noise amplifier (LNA) circuit. Section 4 concludes the paper.

[0063] The proposed signature test approach is illustrated in FIG. 1. A baseband test signal vt is modulated on a high frequency carrier and is applied to the DUT. Output of the DUT is demodulated and filtered so that the resulting signature only has baseband variations. As the applied test signal vt(t) and the demodulated test response vd(t) are both baseband, the proposed test approach obviates the need for an expensive RF tester. Further the modulator and demodulator can easily be designed into the loadboard, leading to an inexpensive test solution.

[0064] A regression model built between the DUT signature and the DUT measurements allows the prediction of DUT measurements without explicitly testing for them [1]. The process is illustrated in FIG. 2. Several different DUT samples from the IC manufacturing process are considered and the DUT measurements are obtained using a high performance ATE. For each of these samples, an optimized baseband test signal is applied and the test signature is obtained by digitizing samples of the demodulated DUT response.

[0065] The test signal applied to the DUT has to be chosen so as to minimize the error in predicting DUT measurements from the signature response. For this purpose, we use the optimization procedure described in [2]. More specifically, the prediction error for ith measurement, for a small perturbation in process parameters is given by 1${\sigma }_{e\left(i\right)}^2={\sigma }_{p\left(i\right)}^2+{\sigma }_{n\left(i\right)}^2$

[0066] where σp is the least squared error between actual and predicted specifications for a small perturbation in (manufacturing) process parameters, and σn is the error contributed by measurement noise [2]. The objective function to be minimized is obtained as 2$F=\sum _{j=1,\dots ,n}^{}{k}_j\mathrm{where}\begin{array}{cc}{k}_j=1+\frac{\left(1-\frac{{\sigma }_{e\left(i\right)}}{{\sigma }^{*}}\right)}{n}& \mathrm{for}{\sigma }_{\mathrm{ei}}<{\sigma }^{*}\\ =\frac{{\sigma }_{e\left(i\right)}}{{\sigma }^{*}}& \mathrm{for}{\sigma }_{\mathrm{ei}}\ge {\sigma }^{*}\end{array}$

[0067] σ* being the maximum allowed prediction error, and n the number of DUT measurements.

[0068] The resulting objective function is minimized using genetic optimization [6], where successive generations of a piecewise linear test stimulus (encoded as a genetic string) yield decreasing values of the objective function.

[0069] 3.0 Experimental results

[0070] This section presents simulation results for a RF amplifier to illustrate the proposed approach. The application circuit is a 900 MHz low-noise amplifier (LNA) [7]. FIG. 3 shows the schematic for the LNA. For illustration, three measurements were considered: Conversion gain, Noise Figure, and Third-order intercept point. Conversion gain and noise figure performances were measured at 900 MHz while the third-order intercept was measured by applying two input frequencies at 900 MHz and 920 MHz and observing the third-order harmonics at 880 MHz and 940 MHz. The LNA circuit was simulated using the SpectreRF simulator [7]. SpectreRF analyses support efficient calculation of operating point, transfer function, noise and distortion of common RF and communication circuits. The DUT measurements were extracted using the Cadence Open Command Environment for Analysis (OCEAN) [8].

[0071] The objective of our test approach is to replace conventional DUT measurements (requiring an expensive RF ATE) with a signature test that can be applied using a low-cost ATE for production test of the DUT. The proposed signature test has to be effective throughout the range of variation expected in the manufacturing process of the DUT. For the circuit in FIG. 3, the important process variations comprise of variation in the values of the resistors, capacitors and the BJT model parameters. For BJTs, the following model parameters were considered: saturation current (Is), Forward current gain (βf), Forward early voltage (Vaf), base resistance (rb), current corner for beta (ikf). Other BJT parameters were found to have negligible impact on the behavior of the LNA circuit. We further assume the parameter variations to be uniformly distributed around their nominal values.

[0072] Following the ATPG approach described in Section 2, a linear prediction model is built to predict the LNA specifications from its signature response, obtained from FIG. 1. For modulation and demodulation, a 10 dBm, 900 MHz RF carrier is chosen. The demodulated DUT response is then passed through a low pass filter with a cutoff frequency of 10 MHz. The DUT signature is obtained by sampling the filtered response at the nyquist rate (20 MHz).

[0073] A genetic optimization algorithm is then used to synthesize a piecewise linear test stimulus for minimizing the least squared error between the actual and predicted specifications for a small perturbation in the process parameters. Further, to keep the simulation time short, the test signal is constrained to be of 5 us duration. FIG. 4 shows an optimized test stimulus after running 10 iterations of the genetic algorithm. FIG. 5 shows the signature of 100 sample circuits in response to the applied test stimulus.

[0074] To validate the proposed signature test, we considered several circuit instances obtained by sampling the uniformly distributed process parameters. For correlation, a multivariate regression model was built between the DUT measurements (conversion gain, noise figure and IP3) and the signature responses for 200 circuit instances. Thereafter, DUT measurements for 100 more circuit instances were predicted from their signatures using the correlation model. FIG. 6 shows the prediction results assuming a +25% uniform distribution for the process parameters. Measured values of conversion gain, noise figure and IP3 for the 100 circuit instances obtained by direct simulation are shown by a ‘o’ and those predicted by signature test are denoted by a ‘*’. The plots show an excellent agreement between direct measurements and those predicted using signature test. The attractive feature of our technique is that these results were obtained using an extremely short duration (5us) test signal, promising significant savings in test costs.

[0075] FIG. 7 shows similar plots for a wider (±50%) process distribution. In reality, most modem IC manufacturing processes are more tightly controlled. The results suggest that even for IC fabs with wide process spreads, the proposed signature test technique holds considerable promise.

[0076] FIG. 8 depicts the impact of noise when measuring signature response. The plots show signature test results for noise figure measurements when additive gaussian noise is added to the signature response of the DUT. It can be seen from the results that there is a close agreement between the actual and predicted values of noise figure even with a large (5 mv RMS) measurement noise. The experiment suggests that robust signature test performance is possible in the presence of measurement noise.

[0077] 3.1 Hardware Validation

[0078] For hardware validation of the proposed approach, we built a RF frontend module using a RF2401 monolithic integrated receiver front-end IC from RF MicroDevices. The mixer and lowpass filter modules for generating signature test were obtained from Mini-Circuits. FIG. 9a. shows a picture of the signature test prototype. The DUT signature obtained in response to a sinewave test (500 mV p-p, 2 MHz) is shown in FIG. 9b. We are currently making measurements on several frontend IC samples from RF MicroDevices. We hope to include data from these experiments in the final version of the paper.

[0079] 4.0 Conclusions

[0080] In this paper, we proposed a low-cost technique for the signature testing of RF circuits. The proposed solution can be easily built into a load board that can be interfaced to an inexpensive tester. As the DUT measurements are obtained on a low-cost ATE using an extremely short duration test stimulus, significant savings in production test costs of RF circuits is made possible.

[0081] 5.0 References

[0082] [1] P. N. Variyam and A. Chatterjee, “Specification-driven Test Design for Analog Circuits,” International Symposium on Defect and Fault Tolerance in VLSI Systems, 1999, pp. 335-340, 1998.

[0083] [2] R. Voorakaranam, A. Chatterjee, “Test Generation for Accurate Prediction of Analog Specifications”, IEEE VLSI Test Symposium, pp. 137-142, 2000.

[0084] [3] M. S. Huetmaker, “RF/Analog Test of Circuits and Systems,” IEEE VLSI Test Symp 2000 IEEE Los Alamitos Calif. USA p 179.

[0085] [4] T. Wilson, “Test Challenges for Next-generation RF Devices,” EE Evaluation Engineering Vol. 39, No. 11, 2000, pp. 31-37.

[0086] [5] US Provisional Patent Application No. 2292PR, “Test Generation for High Frequency and RF Circuits”, April, 2000.

[0087] [6] D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison Wesley, 1989.

[0088] [7] Cadence SpectreRF Simulator User Guide.

[0089] [8] Cadence OCEAN Reference Guide.

[0090] [9] http://www.rfmd.com/DataBooks/db97/2401.pdf

Claims

1. A method for low cost signature testing of electronic circuits produced by a manufacturing process subject to process variations and characterized by a selected set of performance parameters, comprising the steps of: constructing a model for predicting said performance parameters for a first electronic circuit produced by the manufacturing process as a result of receiving the output of one or more second electronic circuits produced by the manufacturing process and stimulated with a selected test stimulus; providing said output to said model; obtaining a prediction of said performance parameters by use of said model; measuring said performance parameters independently of said model; and iteratively varying said test stimulus to minimize the error between said prediction and the corresponding measured values for said performance parameters, for determining an optimized test stimulus.

2. The method of claim 1, further comprising constructing said model as a linear model.

3. The method of claim 2, further comprising revising said model for at least some of said iterations of said test stimulus.

4. The method of claim 1, further comprising constructing a non-linear model for predicting said performance parameters for a manufactured electronic circuit, including applying the optimized said test stimulus to one or more manufactured training circuits, obtaining respective signature outputs of said training circuits, measuring said performance parameters for said training circuits and relating said signature outputs to the measured said performance parameters for said training circuits.

5. The method of claim 4, further comprising applying the optimized said test stimulus to said manufactured circuit, obtaining a signature output thereof, applying said signature output of said manufactured circuit to said non-linear model, and obtaining a prediction of said performance parameters of said manufactured circuit by use of said model.

6. The method of claim 5, further comprising characterizing said signature outputs of said training circuits, characterizing said signature output of said manufactured circuit, comparing the results of said steps of characterizing with each other to determine a deviation therebetween, comparing said deviation to a predetermined threshold and, if said deviation is greater than said threshold, updating said non-linear model, including relating said signature outputs of said training circuits and said signature output of said manufacturing circuit to the measured said performance parameters for said training circuits and said manufacturing circuit.

7. The method of claim 4, further comprising providing performance specifications for said manufactured circuit, applying the optimized said test stimulus to said manufactured circuit, obtaining a signature output thereof, applying said signature output of said manufactured circuit to said non-linear model, and comparing said output with said performance specifications for determining whether said manufactured circuit fails to meet said performance specifications.

8. The method of claim 5, wherein said step of applying includes modulating an RF carrier with the optimized test stimulus, and wherein said step of obtaining includes demodulating the output of said first electronic circuit by said RF carrier to obtain said signature output.

9. An apparatus for low cost signature testing of electronic circuits produced by a manufacturing process subject to process variations and characterized by a selected set of performance parameters, comprising a computerized model for predicting said performance parameters for a first electronic circuit produced by the manufacturing process as a result of receiving the output of one or more second electronic circuits produced by the manufacturing process and stimulated with a selected test stimulus, a device for iteratively varying said test stimulus, and a computer program adapted to command said device to iteratively vary said test stimulus so as to minimize the error between the performance parameters as predicted by said model and corresponding measured values for said performance parameters, for determining an optimized test stimulus.

10. The apparatus of claim 9, wherein said computerized model is a linear model.

11. The apparatus of claim 10, wherein said computer program is further adapted for revising said model for at least some of said iterations of said test stimulus.

12. The apparatus of claim 9, further comprising a computerized non-linear model for predicting said performance parameters for a manufactured electronic circuit, obtained by applying the optimized said test stimulus to one or more manufactured training circuits, obtaining respective signature outputs of said training circuits, measuring said performance parameters for said training circuits and relating said signature outputs to the measured said performance parameters for said training circuits.

13. The apparatus of claim 12, wherein said device is further adapted to apply the optimized said test stimulus to said manufactured circuit and obtain a signature output thereof, wherein said computer program is adapted to receive said signature output, apply said signature output of said manufactured circuit to said computerized non-linear model, and obtain a prediction of said performance parameters of said manufactured circuit by use of said model.

14. The apparatus of claim 13, wherein said computer program is further adapted for characterizing said signature outputs of said training circuits, characterizing said signature output of said manufactured circuit, comparing the results of said steps of characterizing with each other to determine a deviation therebetween, comparing said deviation to a predetermined threshold and, if said deviation is greater than said threshold, the apparatus further includes an updated computerized non-linear model for replacing said first computerized non-linear model obtained by steps including relating said signature outputs of said training circuits and said signature output of said manufacturing circuit to the measured said performance parameters for said training circuits and said manufacturing circuit.

15. The apparatus of claim 12, wherein said device is further adapted to apply the optimized said test stimulus to said manufactured circuit and obtain a signature output thereof, wherein said computer program is adapted to receive said signature output, apply said signature output to said computerized non-linear model, and compare said output with performance specifications for said manufactured circuit, for determining whether said manufactured circuit fails to meet said performance specifications.

16. The apparatus of claim 13, wherein said device is adapted for modulating an RF carrier with the optimized test stimulus and demodulating the output of said manufactured circuit by said RF carrier to obtain said signature output.

17. The apparatus of claim 16, wherein said device includes a low-pass filter for low-pass filtering the demodulated said output.