Stefan-Cristian Rezeanu et al., “Circuit, Architecture and Method for Reading an Address Counter and/or Matching a Bus Width Through One or More Synchronous Ports”, U.S. Ser. No. 09/531,365, filed Mar. 21, 2000. |
“3.3V 64K and 18 Synchronous QuadPort™ Static RAM”, Cypress Preliminary CY7C0430BV, Cypress Semiconductor Corporation, Mar. 27, 2001, pp. 1-36. |
“3.3V 16K/32K×36 FLE×36™ Asynchronous Dual-Port Static RAM”, Cypress Preliminary CY7C056V/CY7C057V, Cypress Semiconductor Corporation, Nov. 22, 2000, pp. 1-22. |
“Understanding The FLEx36 Dual-Port SRAMs”, Cypress Semiconductor Corporation, Oct. 21, 1999, pp. 1-9. |