Patent Application
20070220352
Test and debug of field programmable gate array (herein “FPGA”) functionality is commonly performed using some number, commonly four to thirty-two, visibility ports or test pins built into the FPGA design. The test pins are specifically included in the FPGA design for test and debug of the internal FPGA architecture and displace what might otherwise be used as a functional FPGA external pin. Accordingly, it is beneficial to minimize the number of visibility ports so that a larger percentage of the FPGA external pins may be used for functional purposes. Because test and debug typically requires more test pins than can practically and cost efficiently be provided, it is known to programmatically select a set of internal FPGA signals for presentation at the test pins. U.S. patent application Ser. No. 10/923,460 entitled “Apparatus and Method for Dynamic Circuit Probing of Field Programmable Gate Arrays” filed Aug. 20, 2004 (herein “the '460 application”), the contents of which are specifically incorporated by reference, discloses programmatic selection of internal FPGA signals for routing to the external FPGA test pins for purposes of test and debug using a logic analyzer. Debug, therefore, becomes an iterative process with different FPGA signals routed to the test pins at each iteration and collection and presentation of the collected data using an external logic analyzer.
Also known is provision of an FPGA logic analyzer core for incorporation into the FPGA. The logic analyzer core is provided as part of the FPGA for the specific purpose of test and debug. The logic analyzer core provides simple triggering and limited capture of FPGA digital signals that are not available external of the FPGA. After the trigger and capture, the stored data may be downloaded to a computer and displayed. A user of the logic analyzer core conducts an iterative debug where different internal signals are routed to the logic analyzer core for capture and display. Because memory dedicated to the logic analyzer core is not available as part of the FPGA final functionality, one challenge with the on-chip logic analyzer is that memory depth is limited for purposes of test and debug and only a limited amount of test data may be captured at each iteration. Another challenge is that incorporation of the logic analyzer core into an FPGA can change the FPGA line routing, relative timing and, therefore, the operation of the device.
Some FPGA test and debug tasks benefit from the fully featured external logic analyzer. While it is possible to implement additional features in the logic analyzer core, the increase in logic analyzer core features, requires a larger core adding cost and complexity to the detriment of the final FPGA product.
There is a need, therefore, to combine the benefits of access to internal FPGA signals consistent with a logic analyzer core with the benefits provided by a fully featured external logic analyzer.
An understanding of the present teachings can be gained from the following detailed description, taken in conjunction with the accompanying drawings of which like reference numerals in different drawings refer to the same or similar elements.
In the following detailed description, for purposes of explanation and not limitation, example embodiments disclosing specific details are set forth in order to provide an understanding of the present teachings. However, it will be apparent to one having ordinary skill in the art having had the benefit of the present disclosure that other embodiments according to the present teachings that depart from the specific details disclosed herein remain within the scope of the appended claims. Moreover, descriptions of well-known apparatus and methods may be omitted so as to not obscure the description of the example embodiments. Such methods and apparatus are considered to be within the scope of the present teachings.
With specific reference to
The Ttrace core 104 as part of the FPGA fabric has connection to internal signals 105 of the FPGA. The internal signals 105 originate from one or more system on a chip 102 comprising one or more FPGA cores 106a, 106b, 106c, 106d. The internal signals 105 are those signals, also referred to as communications lines that are used to interconnect constituent circuitry of the FPGA, but are not available as signal pins external to the FPGA. In a specific embodiment, there are a number of test pins 121 that are made available for probing by external measurement equipment and are dedicated to test and debug. The test pins 121 may not be useful once debug is complete. Therefore, there is incentive to minimize the total number of test pins 121 on an FPGA so that more pins may be made available for normal FPGA operation and integration into a system. The Ttrace core 104 accepts the internal signals 105 and programmatically connects one or more of the internal signals 105 to the test pins 121 of the FPGA 101. A test signal bus 122 is then able to carry test signals from the test pins 121 of the FPGA 101 to the data measurement component 112 of the logic analyzer 110.
The Ttrace core 104 is programmed and monitored by the control component 114 through connection 120 via a communications port 202 on the FPGA 101. The control component 114 maintains dialogue with Ttrace status and control core registers 313 to monitor and control the Ttrace core 104 functionality via the communications port 202. The communications port 202 is also used to download status and data from the Ttrace core. In a specific embodiment, the communications port 202 is a serial communications bus operating in accordance with any of a number of serial communication standards, such as IEEE 1149.1, commonly referred to as JTAG. Beneficially, the JTAG standard provides for low bandwidth, ready availability, knowledge base in the industry, and straightforward integration with FPGA fabric.
With specific reference to
A plurality of external signal banks 151a-151c and a plurality of internal signal banks 152a-152c accept signals delivered by the signal router 150. The internal and external signal banks 151, 152 can be any width. In a specific embodiment, all internal signal banks 152 are the same width and all external signal banks 151 are the same width. Information regarding the width of each of the signal banks 151, 152 is stored is the status and control registers 313 for download into the control component 114. The control component 114 is then able to understand the Ttrace core configuration and proceed accordingly. Beneficially, the flexibility of the Ttrace core configuration permits the control component 114 to automatically adapt to different Trace core configurations. Commonly, but not necessarily, the external signal bank 151 has a width equal to a number of test pins 121 that are available from the Ttrace core 104. Commonly, but not necessarily, the internal signal banks 152 have a width equal to a width of internal test memory storage 154. As an example, the external signal bank can be 16 pins wide and the internal signal bank 152 can be 1024 pins wide. The signal router 150 is programmed with the core registers 313 to connect at least one of the signals from the signal buffers 302 to any number of the external and internal signal banks 151, 152. Specifically, the router 150 is able to connect any one of the signals from the signal buffers 302 to anywhere from all to none of the external and internal signal banks 151, 152. Beneficially, the router 150 provides extensive flexibility in defining the type of data for collection during the test and debug operations.
The external and internal signal banks 151, 152 define which of the internal signals 105 may be captured by the logic analyzer 110 through the test pins 121, which of the internal signals 105 may be captured by the internal memory 154, and which grouping of the internal signals are used to establish trigger criteria. The external and internal signal banks 151, 152 connect to comparator 155. The comparator 155 is programmed by the control component 114 of the logic analyzer via the communications port 202 and core registers 313. The core registers 313 specify one of the signal banks 151 or 152 as a trigger source and also specify a digital pattern against which the values of the trigger source are compared. When the specified pattern for the trigger source is presented at the comparator 155 during a test, the comparator 155 initiates trigger signal 156. The trigger signal 156 is presented at one of the test pins 121 and is connected to the logic analyzer 110 via a signal bus 122 from the test pins 121. In a specific embodiment, the trigger signal 156 is a single pulse and it positions the data collected by the logic analyzer 110 in time for a single run of a test.
External signal multiplexer 157 and internal signal multiplexer 158 accept the external signal banks 151 and internal signal banks 152, respectively. Both the external and internal signal multiplexers 157, 158 are programmed via the core registers 313 to select one of the external and internal signal banks 151, 152 for presentation at the outputs of the multiplexers 157, 158. A width of the registers that control the internal and external signal multiplexers 157, 158 is defined by the number of inputs available at each multiplexer's input. Each multiplexer 157, 158, therefore, presents one of its respective inputs at its respective outputs. The external signal multiplexer 157 also accepts an output of a test component 159. The external signal multiplexer 157 presents at its output, the selected external signal bank 151 or test component output to a time domain multiplexer module 159. The function and purpose of the test component and time domain multiplexer module is described in the '460 patent application.
The output of the time domain multiplexer module 160 is connected to test pin port 153. The test pin port 153 is connected to the test pins 121 of the FPGA 101 through the core registers 313. If time domain multiplexing is not used, the output of the external signal multiplexer 157 is presented at the test pin port 153 at a frequency defined by the clock 322. The clock 322 is also presented as one of the test pins 121. In one embodiment, there is a dedicated test pin 121 for the clock 322. In another embodiment, the clock 322 is presented to the signal buffers 302, routed through router 150, and made available as one or more of the signals at the test pin port 153. The logic analyzer 110 collects state data from the test pins 121 using the clock 322. Upon receipt of the trigger signal 156, also presented as one or more of the test pins 121, the logic analyzer 110 is able to position the collected data in time relative to the trigger signal 156. As one of ordinary skill in the art appreciates, the logic analyzer 110 may be programmed to collect data and position the trigger signal at the beginning, middle or end of the collected data.
The output of the internal memory multiplexer 158 is connected to internal memory 154. The internal memory 154 is part of or accessible by the Ttrace core 104 and may comprise either block RAM or distributed memory. In most cases, the amount of memory is limited because it takes space on the FPGA that would otherwise be dedicated to FPGA functions not associated with test and debug. It is possible, however, to collect data from a large number of internal signals 105 in the internal memory 154 because it does not require use of any of the test pins 121. Beneficially, therefore, there is visibility into the internal pin signal activity without using the dedicated test pins 121. The trigger signal 156 is also delivered to the internal memory 154 and upon receipt of the trigger signal 156, data from the output of the internal signal multiplexer 158 is collected in the internal memory 154. When internal signal data collection is complete, the contents of the internal memory 154 are sent to the logic analyzer 110 via the core registers 313 and communications port 202.
The logic analyzer 110, therefore, receives data collected from the output pins 153 of the FPGA 104 and data collected from the internal memory 154 of the FPGA 104. It is desirable to synchronize in time, the data collected in internal memory 154 with the data collected in external memory. In a specific embodiment, data collection into internal memory may begin before the trigger signal 156 and data is presented at the output pins 513 of the FPGA 104. In a specific embodiment, the asserted trigger signal 156 initiates data collection into internal memory 154. In specific embodiments of the Ttrace core 104, there may be a number of cycles of the clock 322 before the trigger signal 156 and data is presented at the test pins 121. The difference in clock cycles between the time the trigger 156 initiates internal data collection and the time the trigger 156 is presented with the data at the output pins 121 comprises a trigger delay. The trigger delay is deterministic and repeatable depending upon a specific design of the Ttrace core 104. In a specific embodiment, therefore, the trigger delay represented as a number of clock cycles is stored as one of the core registers 313. The logic analyzer 110 accesses the trigger delay via the communications port 202 and based upon the delay value in the core register 313 that represents the trigger delay, is able to accurately position the data collected in internal memory relative to the trigger signal 156 and the data collected by the logic analyzer 110 from the test pins 121. In another specific embodiment, there is a deterministic and repeatable first delay between assertion of the trigger signal 156 and initiation of data collection into the internal memory and a deterministic and repeatable second delay between assertion of the trigger signal 156 and presentation of the trigger signal 156 and data at the external pins 121. In this embodiment, two different core registers 313 are made available via the communications port 202 for access by the external logic analyzer for the purpose of properly time correlating the data collected in internal and external memory relative to the trigger signal 156.
With specific reference to
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Trigger options according to the present teachings include specifying trigger criteria for one or more of the internal signal banks 152. The trigger criteria may be established via a graphical user interface (“GUI”) by entering a trigger state into one or more trigger state input frames 504 associated with established internal signal banks 152. When the trigger criteria are met during run time, the Ttrace core 104 asserts the trigger signal 156. In a specific embodiment, the user is able to configure internal data collection relative to the trigger signal 156 so that the trigger signal 156 is positioned at the beginning middle or end of the acquisition. As shown in the example, a trigger signal positioned at 50% pre-store is located in the center of the collected data. Based upon a priori knowledge of the data collection rate and the total amount of internal memory 154, the logic analyzer 110 is able to determine where to place the data collected in internal memory relative to the trigger signal 156. Data is also collected in the external memory relative to the trigger signal 156. As an example, data may be collected immediately upon receipt of the trigger signal 156 or the trigger signal 156 may arm the logic analyzer 110 to trigger on different established criteria based upon data collected from the test pins 121. The arming criteria may be defined in a similar fashion based on input into the trigger state input frames 504. In the example, timing relative to the trigger signal 156 is known for both the internal data collection and external data collection. In this way, the external logic analyzer 110 is able to time correlate the data collected in the internal memory 154 relative to data collected externally. As one of ordinary skill in the art appreciates from a review of
With specific reference to
Embodiments of the teachings are described herein by way of example with reference to the accompanying drawings describing a Ttrace core and its constituent elements. Other variations, adaptations, and embodiments of the present teachings will occur to those of ordinary skill in the art given benefit of the present teachings. For example, the present teachings may be adapted for application to an application specific integrated circuit (“ASIC”). While ASICs are not as readily reconfigurable as FPGAs, the present teachings may be adapted to a non-iterative test process for an ASIC.
