BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a conventional metastability protection circuit;
FIG. 2 illustrates a metastability protection circuit incorporating features of the present invention;
FIG. 3 illustrates the random circuit of FIG. 2 in further detail;
FIGS. 4A and 4B, collectively, illustrate exemplary Verilog Register Transfer Language code incorporating features of the present invention; and
FIG. 5 is a flow chart describing an exemplary signal delay modeling process incorporating features of the present invention.
DETAILED DESCRIPTION
FIG. 1 illustrates a conventional metastability protection circuit 120. As shown in FIG. 1, a signal associated with a first clock domain, CLKa, is applied to a first flip flop 110, for example, in a launching clock domain. The incoming signal needs to cross, for example, from the launching clock domain, CLKa, to a receiving clock domain, CLKb. As indicated above, the clock signals of the launching clock domain, CLKa, and the receiving clock domain, CLKb, may be different frequencies or have the same frequency. The phase relationship between these clock signals, however, is often unknown (i.e., the clock signals are asynchronous). The two frequency clocks, CLKa and CLKb, are normally simulated to be clocks with a common frequency factor. For example, CLKa can have a frequency of 5 MHz, while CLKb has a frequency of 10 MHz. In an actual environment, however, these clocks could be 5 MHz and 7 MHz, or 5 MHz and 5.2 MHz
In order to prevent metastability during the cross-over, a metastability protection circuit 120 is often employed. The exemplary metastability protection circuit 120 comprises one or more D type flip-flops 130-1 and 130-2. As shown in FIG. 1, the D type flip-flops 130 include one input signal D, an output signal Q, and one clock signal CLK. The D type flip-flops 130-1 and 130-2 latch the input signal based on a rising or falling edge of an input clock signal.
As previously indicated, the metastability protection circuit 120 reduces the likelihood of encountering a metastable state. There is currently little, if any, understanding of the effects caused by metastability protection circuit 120 to the overall digital design.
The present invention provides methods and apparatus for simulating the effects of the variable delays caused by the metastability protection circuit 130 of FIG. 1. The present invention allows the behavior of a digital design to be observed by introducing a random transition delay. The random transition delay associated with the metastability protection circuit 120 can thus be introduced during a simulation stage so the effects of the random transition delay can be evaluated on the downstream logic. The disclosed randomization logic allows a designer to simulate the timing effects of metastability in such a way that the delay effects that might be caused by metastablity can better be simulated, and as such, make for a more robust and error free design.
According to a further aspect of the invention, the randomizer logic employed to simulate a random transition delay is only present during a simulation stage and is removed from the end product. Thus, in the exemplary embodiment described herein, the disclosed randomization logic can be switched on and off, and also, is designed, for example, in Register Transfer Language (RTL) such that it poses no problem for a synthesis tool chosen by the design team.
FIG. 2 illustrates a metastability protection circuit 200 incorporating features of the present invention. The exemplary D type flip flops 110, 130-1 and 130-2 shown in FIG. 2 operate in a similar manner to those described above in conjunction with FIG. 1. As shown in FIG. 2, the exemplary metastability protection circuit 200 includes a random circuit 300, discussed further below in conjunction with FIG. 3, a D type flip flop 210 and an edge detection circuit 220. Generally, the random transition delay is generated by the random circuit 300 based upon the detection of an edge by the edge detection circuit 220. The input signal sbit_i is applied to the D input of the D type flip flop 210 that is clocked by the receiving clock domain, CLKb. The flip flop 210 captures the input signal sbit_i. The previous, and current values of the input signal sbit_i are compared on either side of the flip flop 210 so that the rise/fall signal that controls the random transition delay injection knows when to operate.
The exemplary logic shown in the edge detection circuit 220 comprises a pair of AND gates, each having one inverted input and an OR gate. Each AND gate processes the input and output values of the flip flop 210. The upper AND gate is configured to detect a falling edge on sbit_i (input is low and output is high) and the lower AND gate is configured to detect a rising edge on sbit_i (input is high and output is low). Whenever the value on the D input (sbit_i) of flip flop 210 differs from the Q output of flip flop 210, one of the AND gates will have a high output value and then the output of the OR gate will be high. The output of the edge detection circuit 220, random_select, is applied to the random circuit 300 of FIG. 3.
In one exemplary implementation, the random circuit 300, D type flip flop 210 and edge detection circuit 220 portions of the metastability protection circuit 200 are only present during a simulation stage and are removed during synthesis of the RTL to gates.
FIG. 3 illustrates the random circuit 300 of FIG. 2 in further detail. Generally, the random circuit 300 ensures that a random transition delay is only introduced upon detection of an edge by the edge detection circuit 220 of FIG. 2. As shown in FIG. 3, the exemplary random circuit 300 is a multiplexer that selects the sbit_i input shown in FIG. 2 unless an edge is detected by the edge detection circuit 220. When an edge is detected by the edge detection circuit 220, the multiplexer 300 selects the “1” input which receives a pseudo random value of 1 or 0 generated by a $random function. The $random function is discussed further below in conjunction with FIG. 4B. The random circuit 300 thus adds a random transition delay to the incoming control signal that crosses between two clock domains. In this manner, the timing variations inherent in clock domain crossing metastability protection circuits can be simulated.
FIGS. 4A and 4B, collectively, illustrate exemplary Verilog RTL code 400 incorporating features of the present invention. The exemplary code 400 is synthesizable with the Synopsys DesignCompiler software. The code 400 defines an exemplary embodiment of the randomized delay metastability protection circuit 200 of FIG. 2.
As previously indicated, the random circuit 300, D type flip flop 210 and edge detection circuit 220 portions of the metastability protection circuit 200 are only present during a simulation stage. The random circuit 300, D type flip flop 210 and edge detection circuit 220 can be removed during synthesis of the RTL by setting the parameter NORMAL in portion 410 of the code 400 to ‘1’. Likewise, in order to get the randomizing logic to work, the parameter NORMAL in portion 410 should be set to ‘0’ during simulation of the circuit. In this manner, the flip flop d1_real (210), for example, is part of the circuit during simulation. As shown in FIG. 4B, a portion 420 of the code 400 defines the operation of the random circuit 300 that introduces the random transition delay upon detection of a transition of sbit_i during a simulation.
FIG. 5 is a flow chart describing an exemplary signal delay modeling process 500 incorporating features of the present invention. As shown in FIG. 5, the signal delay modeling process 500 initially performs a test during step 510 to determine if during a simulation state, the value of NORMAL is set to ‘1’ indicating that the random delay should be removed, for example, during synthesis.
If it is determined during step 510 that the value of NORMAL is not set to ‘1,’ then a random transition delay is introduced into the signal during step 520 upon detection of an edge in the signal. If, however, it is determined during step 510 that the value of NORMAL is set to ‘1,’ then a random transition delay is not introduced into the signal during step 530.
While exemplary embodiments of the present invention have been described with respect to digital logic blocks, as would be apparent to one skilled in the art, various functions may be implemented in the digital domain as processing steps in a software program, in hardware by circuit elements or state machines, or in combination of both software and hardware. Such software may be employed in, for example, a digital signal processor, micro-controller, or general-purpose computer. Such hardware and software may be embodied within circuits implemented within an integrated circuit.
Thus, the functions of the present invention can be embodied in the form of methods and apparatuses for practicing those methods. One or more aspects of the present invention can be embodied in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, or transmitted over some transmission medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code segments combine with the processor to provide a device that operates analogously to specific logic circuits.
It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.
Patent Application
20080069277
