METHOD AND APPARATUS FOR PHASE CURRENT BALANCING IN A MULTI-PHASE DC-TO-DC CONVERTER

Abstract

A multi-phase DC-to-DC controller is provided. The controller includes a plurality of current sense circuits that sense current in respective converter cell of the converter, and generate respective current sense signals, an averaging circuit that receives the respective current sense signals and generates an average signal, a plurality of error detector circuits that compare respective current sense signals with the average signal and generate respective voltage imbalance signals, a plurality of transconductor circuits that convert respective voltage imbalance signals to respective current imbalance signals, and a plurality of pulse width modulation (PWM) generators that output PWM signals to control respective converter cells based on a comparison between a ramp threshold voltage of the PWM generators and a PWM ramp voltage that is based on the sum of one of the respective current imbalance signals and a first current that is proportional to the input voltage.

Description

TECHNICAL FIELD

The present disclosure generally relates to multi-phase DC-to-DC converters and more particularly to a method and apparatus for achieving output current balance between phases.

BACKGROUND

In a multi-phase DC-to-DC power converter, balance between currents in all phases needs to be considered. Imbalance in output current between phases can cause uneven heat distribution, which adversely affects performance, power efficiency, and size of the power converter. Pulse-width modulation (PWM) control of multiple continuous conduction-mode (CCM) power converters configured to share a common load will not necessarily achieve sharing the output current equally between these converters. A consideration should be taken in the control method to achieve the current balance between phases.

Voltage Mode Control-based (VMC) converters have been popular for their exceptional noise immunity, simple single loop control, and ability to control relatively short on-time periods. Numerous schemes have been proposed for achieving output current balance between phases by altering the duty ratio of a phase in proportion with the deviation of its current from the average of all phases. FIG. 1 depicts an example of such a prior-art DC-to-DC VMC controller, wherein the inductor current of each of N phases, IL₁˜IL_N, is monitored by a respective current sense amplifier 101 and compared by a respective error detector circuit 105 to an average current of all N phases V_CS(AV) derived by an averaging circuit 102 after passing respective low-pass pass filters 103. The resulting imbalance voltage, ΔV_CS1˜ΔV_CSN, is subtracted from a ramp threshold voltage V_COMP of a PWM generator 107 at a respective difference circuit 106. The ramp threshold voltage V_COMP is generated by an error amplifier circuit 110 as a function of the error between the output voltage V_OUT and a fixed reference voltage V_REF, and the ramp voltage of each respective PWM generator 107 is generated from a current through a timing resistor R_T, the amplitude of which is proportional to the input voltage V_IN (input feed forward) of the power converter. Alternatively, the timing resistor R_T could be replaced with a current source that is proportional to the input voltage V_IN.

Due to the presence of significant switching ripple component in the inductor current, low-pass filters 103 are required to achieve current balancing. These filters affect the current balancing loop dynamics and, therefore, degrade the load transient response.

SUMMARY

According to an aspect of one or more exemplary embodiments, a multi-phase DC-to-DC controller for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC converter cells is provided. The controller may include a plurality of current sense circuits each configured to sense current in a respective one of the plurality of converter cells, each of the plurality of current sense circuits configured to generate a respective current sense signal, an averaging circuit configured to receive each of the respective current sense signals and generate an average signal that represents an average of the respective current sense signals, a plurality of error detector circuits each configured to compare a respective current sense signal with the average signal and generate a respective voltage imbalance signal, a plurality of transconductor circuits each configured to convert a respective voltage imbalance signal to a respective current imbalance signal, and a plurality of pulse width modulation (PWM) generators each configured to output a PWM signal configured to control a respective one of the plurality of converter cells based on a comparison between a ramp threshold voltage of the plurality of PWM generators and a PWM ramp voltage that is based on a sum of one of the respective current imbalance signals and a first current that is proportional to the input voltage.

According to one or more exemplary embodiments, each of the plurality of PWM generators may include a source of the first current, which may be a timing resistor configured to generate the first current that is proportional to the input voltage. Alternatively, each of the PWM generators may include a current source that generates the first current in proportion to the input voltage. Each of the plurality of PWM generators may also include a timing capacitor configured to integrate a sum of the first current and a respective current imbalance signal and generate the PWM ramp voltage, and a comparator for outputting a PWM signal based on whether the PWM ramp voltage exceeds the ramp threshold voltage. The first current may be substantially proportional to the input voltage.

According to one or more exemplary embodiments, the controller may include a plurality of multiplier-divider circuits each configured to multiply a respective voltage imbalance signal by a ratio of the input voltage and the ramp threshold voltage, and to generate a respective normalized voltage imbalance signal. The respective voltage imbalance signal converted by each of the plurality of transconductor circuits may be the normalized voltage imbalance signal generated by the plurality of multiplier-divider circuits.

According to one or more exemplary embodiments, the controller may include a ramp threshold voltage generator circuit configured to generate the ramp threshold voltage based on a comparison between the output voltage and a reference voltage.

According to another aspect of one or more exemplary embodiments, there is provided a method in a multi-phase DC-to-DC controller for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC converter cells. The method may include sensing current in a respective one of the plurality of converter cells and generating a respective current sense signal, generating an average signal that represents an average of the respective current sense signals, comparing a respective current sense signal with the average signal and generating a respective voltage imbalance signal, converting a respective voltage imbalance signal to a respective current imbalance signal, and outputting a PWM signal configured to control a respective one of the plurality of converter cells based on a comparison between a ramp threshold voltage and a PWM ramp voltage that is based on a sum of one of the respective current imbalance signals and a first current that is proportional to the input voltage.

The method may further include integrating a sum of the first current and a respective current imbalance signal to generate a PWM ramp voltage, and outputting a PWM signal based on whether the PWM ramp voltage exceeds the ramp threshold voltage. The first current may be substantially proportional to the input voltage.

According to one or more exemplary embodiments, the method may further include multiplying a respective current imbalance signal by a ratio of the input voltage and the ramp threshold voltage to generate a normalized voltage imbalance signal. Converting a respective voltage imbalance signal to a respective current imbalance signal may include converting the normalized voltage imbalance signal to a normalized respective current imbalance signal. The ramp threshold voltage of the PWM generator may be generated based on a comparison between the output voltage and a reference voltage.

According to another aspect of one or more exemplary embodiments, there is provided a multi-phase DC-to-DC controller for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC converter cells. The controller may include a plurality of current sense circuits each configured to sense current in a respective one of the plurality of converter cells, each of the plurality of current sense circuits configured to generate a respective current sense signal, an averaging circuit configured to receive each of the respective current sense signals and generate an average signal that represents an average of the respective current sense signals, a plurality of error detector circuits each configured to compare a respective current sense signal with the average signal and generate a respective voltage imbalance signal, a plurality of multiplier-divider circuits each configured to multiply a respective voltage imbalance signal by a ratio of the input voltage and a ramp threshold voltage to generate a respective normalized voltage imbalance signal, a plurality of transconductor circuits each configured to convert a respective normalized voltage imbalance signal to a respective normalized current imbalance signal, a plurality of pulse width modulation (PWM) generators each configured to output a PWM signal configured to control a respective one of the plurality of converter cells based on a comparison between the ramp threshold voltage and a PWM ramp voltage that based on a sum of one of the respective normalized current imbalance signals and a first current that is proportional to the input voltage, and a ramp threshold voltage generator circuit configured to generate the ramp threshold voltage based on a comparison between the output voltage and a reference voltage. Each of the plurality of PWM generators may include a source of the first current that is proportional to the input voltage, which may be include a timing resistor coupled to the input voltage to generate the first current, a timing capacitor configured to integrate a sum of the first current and a respective current imbalance signal and generate a PWM ramp voltage, and a comparator for outputting a PWM signal based on a comparison between the PWM ramp voltage and the ramp threshold voltage.

BRIEF DESCRIPTION OF DRAWINGS

A more complete understanding of the present embodiments, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

FIG. 1 shows a circuit diagram of a prior art DC to DC controller;

FIG. 2 shows a circuit diagram of a DC to DC controller according to an exemplary embodiment;

FIG. 3 shows a PWM generator including a multiplier-divider circuit configured to normalize the current balancing loop gain of the DC to DC controller according to an exemplary embodiment; and

FIG. 4 shows a circuit diagram of a DC to DC controller according to an exemplary embodiment.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 2 illustrates a multi-phase DC-to-DC controller according to an exemplary embodiment. The multiphase DC to DC controller is implemented as a VMC controller, particularly suitable for use as a buck converter with a plurality of buck-converter cells. The exemplary converter is configured to receive an input voltage and deliver an output voltage to a load by splitting the load current between a plurality of DC-to-DC converter cells (not shown). In this exemplary embodiment, the multi-phase DC-to-DC controller includes respective current sense amplifiers 101, each of which monitors the inductor current of a respective one of N phases, IL₁˜IL_N and senses current in the respective one of a plurality of converter cells at respective current sense inputs CS1+, CS1−. Each of the current sense amplifiers 101 is configured to generate a respective current sense signal V_CS1 through V_CSN. Averaging circuit 102 derives an average current for all of the N phases and is configured to receive the respective current sense signals and generate an average signal V_CS(AV) that represents an average of the respective current sense signals received by the averaging circuit 102. In one embodiment, as illustrated, averaging circuit 102 is implemented with a summing circuit arranged to sum the respective current sense signals V_CS1 through V_CSN, followed by a divider circuit arranged to divide the resultant sum by the number of the respective current sense signals. Respective error detector circuits 105 are each configured to compare a respective current sense signal V_CS1 through V_CSN with the average signal V_CS(AV) and generate a respective voltage imbalance signal ΔV_CS1˜ΔV_CSN. As shown in the exemplary embodiment of FIG. 2, the voltage imbalance signals, ΔV_CS1˜ΔV_CSN, may be converted to respective current imbalance signals, I_err1˜I_errN, using a plurality of respective transconductor circuits 108.

The multi-phase DC-to-DC controller shown in the exemplary embodiment of FIG. 2 may also include a plurality of PWM generators 107 configured to generate respective PWM signals PWM1 through PWMN for control of respective ones of the plurality of DC-to-DC converter cells. Each of the plurality of PWM generators 107 may include a source of a first current, which in FIG. 2 may preferably be a first current through timing resistor R_T the amplitude of which is proportional to the input voltage V_IN, a timing capacitor C_T configured to integrate a sum of the first current and a respective current imbalance signal I_err received from a respective transconductor circuit 108 to generate a PWM ramp voltage, and a comparator 109 configured to output the respective PWM signal PWM1 through PWMN based on a comparison of the PWM ramp voltage and a given ramp threshold voltage, e.g., V_COMP. In the embodiment shown, the respective PWM signal is an active high when the respective PWM ramp voltage exceeds the ramp threshold voltage, V_COMP. Although the PWM generators 107 shown in FIG. 2 each include a respective timing resistor R_T coupled between input voltage V_IN and the positive terminal of the comparator 109, each of the PWM generators 107 may alternatively include a current source (as shown in FIG. 4) that generates the first current, the amplitude of which may be proportional to the input voltage V_IN. As shown in FIG. 2, the PWM generator 107 may also include a switch Rst coupled in parallel with timing capacitor C_T, both of which are coupled between the positive terminal of the comparator 109 and ground. The negative terminal of the comparator 109 may be coupled to the ramp threshold voltage V_COMP. The ramp threshold voltage V_COMP is generated by an error amplifier circuit 110 as a function of the error between the output voltage V_OUT and a fixed reference voltage V_REF. The switch Rst may be used to reset the voltage across the timing capacitor C_T responsive to a respective control signal.

As explained above, a respective current imbalance signal I_err1˜I_errN is summed with the first current through the timing resistor R_T at the timing capacitor C_T. Advantageously, integration of respective current imbalance signal I_err1˜I_errN and the first current negates the effect of the ripple current component, and the filters 103 shown in the prior art converter of FIG. 1 can be eliminated, which may improve the load transient response.

According to another exemplary embodiment, preconditioning of the loop gain with respect to V_IN and V_COMP may be achieved. More specifically, the small-signal relationship between {tilde over (d)}, V_COMP, I_err, and V_IN can be given as:

$\begin{array}{cc}\tilde{d}=\frac{R_T{C}_T}{V_{\mathrm{IN}}{T}_S}·\left({\tilde{v}}_{\mathrm{COMP}}-\frac{V_{\mathrm{COMP}}}{V_{\mathrm{IN}}}·{\tilde{v}}_{\mathrm{IN}}-\frac{R_T{V}_{\mathrm{COMP}}}{V_{\mathrm{IN}}}{\tilde{i}}_{\mathrm{err}}\right)& \left(1\right)\end{array}$

where {tilde over (d)} is the small-signal duty ratio of the converter,ĩ_err the small signal change of the current imbalance signal I_errN,{tilde over (v)}_IN is the small signal change of the input voltage V_IN,{tilde over (v)}_COMP is the small signal change of the ramp threshold voltage V_COMP, andT_S is the switching period.

Setting {tilde over (v)}_COMP and {tilde over (v)}_IN to zero, a small-signal relationship between I_err and the steady state switching node voltage V_SW (which is in the subsequent power stage, and not shown in the Figures) can be given as:

$\begin{array}{cc}{\tilde{v}}_{\mathrm{SW}}{\text{|}}_{\underset{{\tilde{v}}_{\mathrm{IN}}=0}{{\tilde{v}}_{\mathrm{COMP}}=0}}=V_{\mathrm{IN}}·\tilde{d}=-\frac{R_T^2{C}_T}{T_S}·\frac{V_{\mathrm{COMP}}}{V_{\mathrm{IN}}}·{\tilde{i}}_{\mathrm{err}}& \left(2\right)\end{array}$

wherein {tilde over (v)}_SW is the small signal voltage change at the switching node.

By pre-conditioning I_err with respect to V_COMP/V_IN, a constant current share loop gain can be achieved at any V_COMP and V_IN.

FIG. 3 shows a PWM generator 107 according to an exemplary embodiment that may achieve constant current share loop gain at any V_COMP and V_IN. Referring to FIG. 3, the exemplary multi-phase DC-to-DC VMC controller may include a plurality of multiplier-divider circuits 100 whose outputs are respectively coupled to the transconductor circuits 108, and are configured to normalize the current balancing loop gain. Each of the multiplier-divider circuits 100 of FIG. 3 may receive as inputs a respective imbalance voltage ΔV_CS1, input voltage V_IN, and ramp threshold voltage V_COMP. The multiplier-divider circuit 100 may multiply the respective imbalance voltage ΔV_CS1 by the input voltage V_IN, and divide the respective imbalance voltage ΔV_CS1 by the ramp threshold voltage V_COMP. As shown in FIG. 3, the resulting voltage may be input to the transconductor circuit 108, which converts the input voltage to a respective current imbalance signal I_err1˜I_errN.

Accordingly, Equation (2) may be modified as follows:

$\begin{array}{cc}{\tilde{v}}_{\mathrm{SW}}{\text{|}}_{\underset{{\tilde{v}}_{\mathrm{IN}}=0}{{\tilde{v}}_{\mathrm{COMP}}=0}}=V_{\mathrm{IN}}·\tilde{d}=\frac{R_T^2{C}_T·g_m}{T_S}·{\tilde{v}}_{\mathrm{CS}}& \left(3\right)\end{array}$

where g_m is the gain of the transconductor circuit 108, and {tilde over (v)}_CS is the small signal change of a respective current sense signal output by a respective current sense amplifier 101. As shown in Equation (3), the gain R_T²C_Tg_m/T_S may be invariant with respect to V_IN and V_COMP. Thus, in this exemplary embodiment, the multi-phase DC-to-DC controller may include a plurality of multiplier-divider circuits 100, wherein each of the plurality of multiplier-divider circuits 100 is configured to multiply a respective current imbalance signal, i.e., ΔV_CS1˜ΔV_CSN by a ratio of the input voltage and the output voltage, and to generate a normalized current imbalance signal, which may be invariant with respect to V_IN and V_COMP.

Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, all embodiments can be combined in any way and/or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and sub combinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

It will be appreciated by persons skilled in the art that the embodiments described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings.

Claims

1. A multi-phase DC-to-DC controller for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC converter cells, the multi-phase DC-to-DC controller comprising: a plurality of current sense circuits each configured to sense current in a respective one of the plurality of converter cells, each of the plurality of current sense circuits configured to generate a respective current sense signal;an averaging circuit configured to receive each of the respective current sense signals and generate an average signal that represents an average of the respective current sense signals;a plurality of error detector circuits each configured to compare a respective current sense signal with the average signal and generate a respective voltage imbalance signal;a plurality of transconductor circuits each configured to convert a respective voltage imbalance signal to a respective current imbalance signal; anda plurality of pulse width modulation (PWM) generators each configured to output a PWM signal configured to control a respective one of the plurality of converter cells based on a comparison between a ramp threshold voltage of the plurality of PWM generators and a respective PWM ramp voltage that is based on a sum of one of the respective current imbalance signals and a respective first current that is proportional to the input voltage.

2. The multi-phase DC-to-DC controller of claim 1, wherein each of the plurality of PWM generators comprises: a timing resistor configured to generate the respective first current that is proportional to the input voltage;a timing capacitor configured to integrate a sum of the respective first current and the respective current imbalance signal and generate the PWM ramp voltage; anda comparator for outputting a respective PWM signal to activate the respective one of the plurality of converter cells, the respective PWM signal based on a comparison of the PWM ramp voltage and the ramp threshold voltage.

3. The multi-phase DC-to-DC controller of claim 1, further comprising: a plurality of multiplier-divider circuits each configured to multiply a respective voltage imbalance signal by a ratio of the input voltage and the ramp threshold voltage, and to generate a respective normalized voltage imbalance signal;wherein the respective voltage imbalance signal converted by each of the plurality of transconductor circuits is the normalized voltage imbalance signal generated by the plurality of multiplier-divider circuits.

4. The multi-phase DC-to-DC controller of claim 3, further comprising: a ramp threshold voltage generator circuit configured to generate the ramp threshold voltage based on a comparison between the output voltage and a reference voltage.

5. The multi-phase DC-to-DC controller of claim 1, wherein each of the plurality of PWM generators comprises: a current source configured to generate the respective first current that is proportional to the input voltage;a timing capacitor configured to integrate a sum of the respective first current and a respective current imbalance signal and generate the respective PWM ramp voltage; anda comparator for outputting a respective PWM signal configured to control the respective one of the plurality of converter cells, the respective PWM signal based on a comparison of the PWM ramp voltage and the ramp threshold voltage.

6. A method in a multi-phase DC-to-DC controller for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC converter cells, the method comprising: sensing current in a respective one of the plurality of converter cells and generating a respective current sense signal;generating an average signal that represents an average of the respective current sense signals;comparing a respective current sense signal with the average signal and generating a respective voltage imbalance signal;converting a respective voltage imbalance signal to a respective current imbalance signal; andoutputting a PWM signal configured to control a respective one of the plurality of converter cells based on a comparison between a ramp threshold voltage and a respective PWM ramp voltage that is based on a sum of one of the respective current imbalance signals and a first current that is proportional to the input voltage.

7. The method of claim 6, further comprising: integrating a sum of the first current and the respective current imbalance signal to generate a PWM ramp voltage; andoutputting a PWM signal to activate the respective one of the plurality of converter cells based on a comparison of the PWM ramp voltage and the ramp threshold voltage.

8. The method of claim 6, further comprising: multiplying a respective current imbalance signal by a ratio of the input voltage and the ramp threshold voltage to generate a normalized voltage imbalance signal;wherein converting the respective voltage imbalance signal to the respective current imbalance signal comprises converting the normalized voltage imbalance signal to a normalized respective current imbalance signal.

9. The method of claim 8, wherein the ramp threshold voltage of the PWM generator is generated based on a comparison between the output voltage and a reference voltage.

10. A multi-phase DC-to-DC controller for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC converter cells, the controller comprising: a plurality of current sense circuits each configured to sense current in a respective one of the plurality of converter cells, each of the plurality of current sense circuits configured to generate a respective current sense signal;an averaging circuit configured to receive each of the respective current sense signals and generate an average signal that represents an average of the respective current sense signals;a plurality of error detector circuits each configured to compare a respective current sense signal with the average signal and generate a respective voltage imbalance signal;a plurality of multiplier-divider circuits each configured to multiply a respective voltage imbalance signal by a ratio of the input voltage and a ramp threshold voltage to generate a respective normalized voltage imbalance signal;a plurality of transconductor circuits each configured to convert a respective normalized voltage imbalance signal to a respective normalized current imbalance signal; anda plurality of pulse width modulation (PWM) generators each configured to output a PWM signal configured to control a respective one of the plurality of converter cells based on a comparison between the ramp threshold voltage and a respective PWM ramp voltage that based on a sum of one of the respective normalized current imbalance signals and a first current that is proportional to the input voltage;wherein each of the plurality of PWM generators comprises: a timing capacitor configured to integrate a sum of the first current and a respective current imbalance signal and generate the PWM ramp voltage; anda comparator for outputting a PWM signal based on a comparison of the PWM ramp voltage and the ramp threshold voltage.

11. The multi-phase DC-to-DC controller of claim 10, wherein each of the plurality of PWM generators further comprises a timing resistor configured to generate the first current that is proportional to the input voltage.

12. The multi-phase DC-to-DC controller of claim 10, wherein each of the plurality of PWM generators further comprises a current source configured to generate the first current that is proportional to the input voltage.

13. The multi-phase DC-to-DC controller of claim 10, further comprising a ramp threshold voltage generator circuit configured to generate the ramp threshold voltage based on a comparison between the output voltage and a reference voltage.