Memory cells, such as antifuse one-time-programmable (OTP) memory cells, can contain leakage paths that are activated after programming of all the memory cells in a memory array. The activation of leakage paths can be caused by several mechanisms. For example, a leakage path can be caused by a defect that resides in a location that is not electrically visible until the rupture of the antifuse. Once the antifuse is ruptured and a filament is formed, this defect can provide a short circuit between two word lines, between two bit lines, or between a word line and a bit line. A leakage path can also be caused by a slight change in the reverse leakage of programmed memory cells. Even though the memory cells are not selected for read, the unselected reverse leakage adds to the off-current leakage and may trigger an incorrect read of memory cells. A leakage path can also be caused by a slight change in the leakage of weak defects induced by local heating or electromigration during the high-voltage programming. This change can be sufficient to locally either reduce the read voltage or read current during a memory read, causing the incorrect value to be read out. One commonality in each of these mechanisms is that the problem cannot always be detected during the programming of any particular bit but can be detected after programming several bits of the memory array.
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims.
By way of introduction, the preferred embodiments described below provide a method and apparatus for programming a memory array. In one preferred embodiment, word lines in a memory array are programmed. After each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another preferred embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another preferred embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
The preferred embodiments will now be described with reference to the attached drawings.
The main and redundant memory arrays 110, 120 each comprise a plurality of memory cells. The memory cells can take any suitable form and can be write-once (i.e., one-time programmable), write-many, or few-time programmable. The memory cells can be organized in a single layer (i.e., a two-dimensional array) or in a plurality of layers stacked vertically above one another above a single silicon substrate (i.e., a three-dimensional array), as described in U.S. Pat. No. 6,034,882 to Johnson et al. and U.S. Pat. No. 6,420,215 to Knall et al., both of which are assigned to the assignee of the present invention and are hereby incorporated by reference. While the memory cells preferably comprise a semiconductor material, other materials can be used, such as, but not limited to, phase-change materials and amorphous solids as well as those used with MRAM and organic passive element arrays, as described in U.S. Pat. No. 6,055,180, which is hereby incorporated by reference. It is important to note that the following claims should not be read as requiring a specific type of memory device (e.g., write-once or write-many) or specific type of memory array (e.g., two dimensional or three-dimensional) unless explicitly recited therein. An antifuse memory cell, which comprises a series capacitor and diode, will be used to illustrate these preferred embodiments. In the unprogrammed state, the antifuse memory cell does not conduct current, as no current passes through the capacitor. However, when programmed, a filament is formed by breaking down the capacitor, and, in the programmed state, the antifuse memory cell conducts current through the filament.
As described in the background section, a defect can occur in the main memory array 110. As used herein, a “defect” refers to any mechanism that results in the activation of a leakage path that can trigger an incorrect read of a memory cell. Defects include, but are not limited to, defects that reside in a location that is not electrically visible until the rupture of an antifuse in an antifuse memory cell, a defect that results in unselected reverse leakage adding to off-current leakage and triggering an incorrect read of a memory cell, and a defect induced by local heating or electromigration during the high-voltage programming.
The redundancy control logic 130 in
In operation, the redundancy control logic 130 detects whether a defect is present on a word line 140 that has been programmed in the main array 110. If a defect is detected on that word line 140, the word line 140 is repaired with a word line 150 in the redundant array 120. A word line 140 in the main array 110 is “repaired” when a substitute word line 150 in the redundant array 120 takes its place. A redundancy pointer 160 is stored in a location in the main array 110 associated with the bad word line 140. When the memory address of the bad word line 140 is received in conjunction with a read or write operation, the redundancy pointer 160 associated with that word line 140 is read and points the redundancy control logic 130 to the repaired word line 150 in the redundant array 120. U.S. Pat. No. 6,868,022, U.S. Patent Application No. US 2003-0115518 A1, and U.S. patent application Ser. No. 11/024,516, which are all assigned to the assignee of the present invention and are hereby incorporated by reference, provide additional information on preferred and alternate redundancy schemes.
Various mechanisms can be used to attempt to detect a defect on a word line. In one embodiment, information is written to the main memory 110 on a page-by-page basis, and the redundancy control logic 130 comprises a page buffer. (For simplicity, this document will assume that each word line can store one page of information. Of course, other organization schemes can be used.) In operation, after each word line in the main array 110 is programmed with the information stored in the page buffer, the word line is read back, and the information stored in the word line is compared with the information stored in the page buffer. A mismatch between the information read back from the word line and the information stored in the page buffer indicates that a defect (or some other type of error) is present on the word line. As described above, if a defect is detected on a word line in the main array 110, that word line is repaired with a redundant word line in the redundant array 120, and the appropriate redundancy pointer 160 is written in the main array 110. (As mentioned above, instead of or in addition to marking a word line as bad during programming (i.e., “on-the-fly redundancy”), a word line can be marked as bad during production sort.)
One difficulty associated with detecting a defect that affects multiple word lines is that the defect may only be detectable after at least two of those word lines are programmed. Take, for example, the defect 200 shown in
The redundancy control logic 130 can be designed in such a way to address this situation. One embodiment uses a “two-pass” programming solution. In general, consider a memory array having first and second word lines (the terms “first” and “second” are being used generically and do not necessarily refer to the very first and second word lines in the memory array), wherein the first word line comprises a defect that is detectable only after the second word line is programmed (as with word lines A and B in the above example). After each word line is programmed, an attempt is made to detect a defect on that word line, and, if a defect is detected, that word line is repaired with a redundant word line. This is considered the first programming pass. A second programming pass is performed, repeating the above acts. Since the second word line has already been programmed in the first programming pass, when the first word line is reprogrammed in the second programming pass, the defect in the first word line is detected, and the first word line is repaired. This embodiment will be illustrated further in conjunction with
After the first pass programming operation ends, a second pass programming operation begins, repeating the acts described above. However, this time, after page 0 is programmed into word line A, a defect is detected because of the short that now exists between word lines A and B (but did not exist the first time word line A was programmed). In response to the defect being detected, word line A is repaired by programming page 0 into a word line in the redundant array 120, and the appropriate redundancy pointer 160 is programmed in the main array 110. The second pass programming operation continues and ends after page 4 is programmed in word line E. Accordingly, the defect on word line B was detected and word line B was repaired during the first programming pass, while the defect on word line A was detected and the word line A was repaired during the second programming pass.
As can be seen by this illustration, this embodiment reduces the bandwidth overhead of doing a complete two-pass programming by avoiding the reprogramming of word lines that do not contain a defect. In other words, this embodiment achieves both high-quality and high-bandwidth programming by reprogramming only the word line that fails first pass programming and the previously-programmed adjacent word line. (In an alternate embodiment, if a defect is detected on a given word line (e.g., word line B), not only is that word line (e.g., word line B) and the previously-programmed adjacent word line (e.g., word line A) repaired, but so is the yet-to-be-programmed adjacent word line (e.g., word line C).)
In yet another embodiment, instead of attempting to detect a defect on the word line that has just been programmed, the redundancy control logic 130 (designed with a sufficiently-large page buffer) can attempt to detect a defect on that word line as well as a previously-programmed adjacent word line.
There are several alternatives that can be used with these preferred embodiments. For example, in the above embodiments, an attempt to detect a defect on a word line was made by reading back a word line and comparing its contents to information stored in a page register. Instead of using a separate read operation to determine if the contents of a word line match that of the page buffer on a word-line-by-word-line basis, the programmed/unprogrammed state of each memory cell can be sensed while attempting to program the memory cell. This sensing-while-programming technique is described in detail in U.S. Pat. No. 6,574,145, which is assigned to the assignee of the present invention and is hereby incorporated by reference. Also, in the embodiments described above, the redundancy control logic 130 provided on-the-fly redundancy/self-repair functionality. In an alternate embodiment, instead of having “on-chip” support for redundancy/self-repair, a host device in communication with the memory device is responsible for redundancy operations. Additionally, it should be noted that the “on-the-fly” self-repair functionality described above can be used either when the main array 110 is being programmed in the field (by an end user) or at the factory (such as when the main array 110 is being programmed with data or is being tested).
Further, the reprogramming can occur with exactly the same conditions or with different margin settings to tailor the reprogram conditions to margin out and thereby repair the memory cells affected by weak defects. The programming of the entire memory may result both in marginal 0's (cells that should be programmed to on-state) because there is a leakage that either reduces the effective voltage or the effective current on the selected bit or in marginal 1's (cells that should be unprogrammed in off-state) because there is a leakage on the selected bit or a bit line that increases the current on the selected bit. Marginal 0's can be detected with low read voltage and/or high read reference current. Marginal 1's can be detected with high read voltage and/or low read reference current. A default programming pass has margins for both 1's and 0's. It is therefore possible to achieve improved yield by simply programming the entire memory twice with the default 1's and 0's margin or by having a different margin for the two passes of programming steps.
It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of this invention. Finally, it should be noted that any aspect of any of the preferred embodiments described herein can be used alone or in combination with one another.
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