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GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/816for an application-specific layout

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor memory devices and repair methods of the semiconducto...
- Patent number 11,621,050
- Issue date Apr 4, 2023
- SK hynix Inc.
- Jae Il Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for fuse latch redundancy
- Patent number 11,257,566
- Issue date Feb 22, 2022
- Micron Technology, Inc.
- Dennis G. Montierth
- G11 - INFORMATION STORAGE
Information Patent Grant
Peripheral logic circuits under DRAM memory arrays
- Patent number 11,031,405
- Issue date Jun 8, 2021
- Micron Technology, Inc.
- Mansour Fardad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Redundancy array column decoder for memory
- Patent number 10,943,633
- Issue date Mar 9, 2021
- Micron Technology, Inc.
- Daniele Vimercati
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for fuse latch redundancy
- Patent number 10,755,799
- Issue date Aug 25, 2020
- Micron Technology, Inc.
- Dennis G. Montierth
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for through substrate via test
- Patent number 10,629,502
- Issue date Apr 21, 2020
- Micron Technology, Inc.
- Ebrahim H Hargan
- G01 - MEASURING TESTING
Information Patent Grant
On-the-fly bit failure detection and bit redundancy remapping techn...
- Patent number 10,529,439
- Issue date Jan 7, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error handling for match action unit memory of a forwarding element
- Patent number 10,515,699
- Issue date Dec 24, 2019
- BAREFOOT NETWORKS, INC.
- Jay E. S. Peterson
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory devices, methods of operating semiconductor me...
- Patent number 10,497,460
- Issue date Dec 3, 2019
- Samsung Electronics Co., Ltd.
- Kyung-Ryun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to...
- Patent number 10,489,245
- Issue date Nov 26, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundancy array column decoder for memory
- Patent number 10,468,085
- Issue date Nov 5, 2019
- Micron Technology, Inc.
- Daniele Vimercati
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to achieve area reduction through co-optimizing logic co...
- Patent number 10,268,122
- Issue date Apr 23, 2019
- Intel Corporation
- Silvio E. Bou-Ghazale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction code (ECC) decoders sharing logic operations, memo...
- Patent number 10,243,588
- Issue date Mar 26, 2019
- SK hynix Inc.
- Soojin Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error handling for match action unit memory of a forwarding element
- Patent number 10,127,983
- Issue date Nov 13, 2018
- BAREFOOT NETWORKS, INC.
- Jay E. S. Peterson
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy array column decoder for memory
- Patent number 10,121,526
- Issue date Nov 6, 2018
- Micron Technology, Inc.
- Daniele Vimercati
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device for controlling having different refres...
- Patent number 10,062,427
- Issue date Aug 28, 2018
- Samsung Electronics Co., Ltd.
- Whi-Young Bae
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for through substrate via test
- Patent number 10,037,926
- Issue date Jul 31, 2018
- Micron Technology, Inc.
- Ebrahim H Hargan
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor apparatus capable of improving efficiency for a circu...
- Patent number 10,020,030
- Issue date Jul 10, 2018
- SK hynix Inc.
- Seung Bong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault-tolerance through silicon via interface and controlling metho...
- Patent number 9,588,717
- Issue date Mar 7, 2017
- Industrial Technology Research Institute
- Chih-Yen Lo
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-port bit cell having increased width
- Patent number 9,536,596
- Issue date Jan 3, 2017
- QUALCOMM Incorporated
- Niladri Narayan Mojumder
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for through substrate via test
- Patent number 9,318,394
- Issue date Apr 19, 2016
- Micron Technology, Inc.
- Ebrahim H Hargan
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips
- Patent number 8,873,320
- Issue date Oct 28, 2014
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for through substrate via test
- Patent number 8,847,619
- Issue date Sep 30, 2014
- Micron Technology, Inc.
- Ebrahim H Hargan
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory having half-column redundancy
- Patent number 8,767,488
- Issue date Jul 1, 2014
- NetLogic Microsystems, Inc.
- Varadarajan Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device for compensating for operating voltage...
- Patent number 8,730,731
- Issue date May 20, 2014
- Samsung Electronics Co., Ltd.
- Ho Jung Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit devices and systems having programmable impedanc...
- Patent number 8,675,396
- Issue date Mar 18, 2014
- Adesto Technologies Corporation
- Narbeh Derhacobian
- G11 - INFORMATION STORAGE
Information Patent Grant
Block mapping circuit and method for memory device
- Patent number 8,645,621
- Issue date Feb 4, 2014
- NetLogic Microsystems
- Dinesh Maheshwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundant memory to mask DRAM failures
- Patent number 8,473,791
- Issue date Jun 25, 2013
- Hewlett-Packard Development Company, L.P.
- Mark Shaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 8,345,494
- Issue date Jan 1, 2013
- Hynix Semiconductor Inc.
- Ki-Myung Kyung
- G11 - INFORMATION STORAGE
Information Patent Grant
Write-once nonvolatile memory with redundancy capability
- Patent number 8,339,832
- Issue date Dec 25, 2012
- Semiconductor Energy Laboratory Co., Ltd.
- Kiyoshi Kato
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Failover Methods and Systems in Three-Dimensional Memory Device
- Publication number 20230176953
- Publication date Jun 8, 2023
- Rambus Inc.
- Joohee Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR FUSE LATCH REDUNDANCY
- Publication number 20200381077
- Publication date Dec 3, 2020
- Micron Technology, Inc.
- Dennis G. Montierth
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY
- Publication number 20200090726
- Publication date Mar 19, 2020
- Micron Technology, Inc.
- Daniele Vimercati
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY
- Publication number 20180374527
- Publication date Dec 27, 2018
- Micron Technology, Inc.
- Daniele Vimercati
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR CORRECTION CODE (ECC) DECODERS SHARING LOGIC OPERATIONS, MEMO...
- Publication number 20180198468
- Publication date Jul 12, 2018
- SK HYNIX INC.
- Soojin KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Systems for Repairing Interior Device Layers in Three-D...
- Publication number 20130168674
- Publication date Jul 4, 2013
- RAMBUS INC.
- Paul D. Franzon
- G11 - INFORMATION STORAGE
Information Patent Application
Nonvolatile Memory And Writing Method Thereof, And Semiconductor De...
- Publication number 20130107645
- Publication date May 2, 2013
- Semiconductor Energy Laboratory Co., Ltd.
- Kiyoshi KATO
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM REPAIR ARCHITECTURE FOR WIDE I/O DRAM BASED 2.5D/3D SYSTEM CHIPS
- Publication number 20130044554
- Publication date Feb 21, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Sandeep Kumar GOEL
- G11 - INFORMATION STORAGE
Information Patent Application
Block Mapping Circuit and Method for Memory Device
- Publication number 20120290782
- Publication date Nov 15, 2012
- NetLogic Microsystems, Inc.
- Dinesh Maheshwari
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20120033515
- Publication date Feb 9, 2012
- Ki-Myung Kyung
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST
- Publication number 20110267092
- Publication date Nov 3, 2011
- Ebrahim H. Hargan
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20110267914
- Publication date Nov 3, 2011
- PANASONIC CORPORATION
- Satoshi ISHIKURA
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor Memory Device
- Publication number 20100290297
- Publication date Nov 18, 2010
- Ki-Myung Kyung
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20100290296
- Publication date Nov 18, 2010
- Joong-Ho Lee
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY AND WRITING METHOD THEREOF, AND SEMICONDUCTOR D...
- Publication number 20100195367
- Publication date Aug 5, 2010
- SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Kiyoshi KATO
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE FOR COMPENSATING FOR OPERATING VOLTAGE...
- Publication number 20100182866
- Publication date Jul 22, 2010
- SAMSUNG ELECTRONICS CO., LTD.
- Ho Jung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
TCAM BIST WITH REDUNDANCY
- Publication number 20100023804
- Publication date Jan 28, 2010
- John A. Wickeraad
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST
- Publication number 20100013512
- Publication date Jan 21, 2010
- Micron Technology, Inc.
- Ebrahim H. Hargan
- G01 - MEASURING TESTING
Information Patent Application
Methods and Apparatus for Translating a System Address
- Publication number 20090240903
- Publication date Sep 24, 2009
- Dell Products L.P.
- William F. Sauber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for SRAM Macro Sparing in Computer Chips
- Publication number 20090106607
- Publication date Apr 23, 2009
- International Business Machines Corporation
- Timothy Carl Bronson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY PERIPHERAL STRUCTURES AND USE
- Publication number 20090073796
- Publication date Mar 19, 2009
- International Business Machines Corporation
- Ishtiaq Ahsan
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANT MEMORY TO MASK DRAM FAILURES
- Publication number 20080270826
- Publication date Oct 30, 2008
- Mark SHAW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRICAL FUSES WITH REDUNDANCY
- Publication number 20080252361
- Publication date Oct 16, 2008
- Taiwan Semiconductor Manufacturing Co., LTD
- Shine Chien Chung
- G11 - INFORMATION STORAGE
Information Patent Application
Self-referencing redundancy scheme for a content addressable memory
- Publication number 20080229154
- Publication date Sep 18, 2008
- James I. Esteves
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM WITH REDUNDANT RAM MEMORY CELLS HAVING A DIFFERENT DE...
- Publication number 20080181034
- Publication date Jul 31, 2008
- Bradford L. Hunter
- G11 - INFORMATION STORAGE
Information Patent Application
Fuse cell array with redundancy features
- Publication number 20080151593
- Publication date Jun 26, 2008
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device
- Publication number 20080074939
- Publication date Mar 27, 2008
- FUJITSU LIMITED
- Katsuhiro Mori
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit device and electronic instrument
- Publication number 20080055324
- Publication date Mar 6, 2008
- SEIKO EPSON CORPORATION
- Satoru Kodaira
- G11 - INFORMATION STORAGE
Information Patent Application
Thin film magnetic memory device having redundant configuration
- Publication number 20080037318
- Publication date Feb 14, 2008
- Renesas Technology Corp.
- Hideto Hidaka
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit memory devices having multi-bit normal memory c...
- Publication number 20070195619
- Publication date Aug 23, 2007
- SAMSUNG ELECTRONICS CO., LTD.
- Hyoung-seub Rhie
- G11 - INFORMATION STORAGE

for an application-specific layout

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor memory devices and repair methods of the semiconducto...

Apparatuses and methods for fuse latch redundancy

Peripheral logic circuits under DRAM memory arrays

Redundancy array column decoder for memory

Apparatuses and methods for fuse latch redundancy

Apparatus and methods for through substrate via test

On-the-fly bit failure detection and bit redundancy remapping techn...

Error handling for match action unit memory of a forwarding element

Semiconductor memory devices, methods of operating semiconductor me...

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to...

Redundancy array column decoder for memory

Techniques to achieve area reduction through co-optimizing logic co...

Error correction code (ECC) decoders sharing logic operations, memo...

Error handling for match action unit memory of a forwarding element

Redundancy array column decoder for memory

Semiconductor memory device for controlling having different refres...

Apparatus and methods for through substrate via test

Semiconductor apparatus capable of improving efficiency for a circu...

Fault-tolerance through silicon via interface and controlling metho...

Three-port bit cell having increased width

Apparatus and methods for through substrate via test

DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips

Apparatus and methods for through substrate via test

Content addressable memory having half-column redundancy

Semiconductor memory device for compensating for operating voltage...

Integrated circuit devices and systems having programmable impedanc...

Block mapping circuit and method for memory device

Redundant memory to mask DRAM failures

Semiconductor memory device

Write-once nonvolatile memory with redundancy capability

Patents Applicationslast 30 patents

Failover Methods and Systems in Three-Dimensional Memory Device

APPARATUSES AND METHODS FOR FUSE LATCH REDUNDANCY

REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY

REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY

ERROR CORRECTION CODE (ECC) DECODERS SHARING LOGIC OPERATIONS, MEMO...

Methods and Systems for Repairing Interior Device Layers in Three-D...

Nonvolatile Memory And Writing Method Thereof, And Semiconductor De...

DRAM REPAIR ARCHITECTURE FOR WIDE I/O DRAM BASED 2.5D/3D SYSTEM CHIPS

Block Mapping Circuit and Method for Memory Device

SEMICONDUCTOR MEMORY DEVICE

APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST

SEMICONDUCTOR MEMORY DEVICE

Semiconductor Memory Device

SEMICONDUCTOR MEMORY DEVICE

NONVOLATILE MEMORY AND WRITING METHOD THEREOF, AND SEMICONDUCTOR D...

SEMICONDUCTOR MEMORY DEVICE FOR COMPENSATING FOR OPERATING VOLTAGE...

TCAM BIST WITH REDUNDANCY

APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST

Methods and Apparatus for Translating a System Address

Method and Apparatus for SRAM Macro Sparing in Computer Chips

MEMORY ARRAY PERIPHERAL STRUCTURES AND USE

REDUNDANT MEMORY TO MASK DRAM FAILURES

ELECTRICAL FUSES WITH REDUNDANCY

Self-referencing redundancy scheme for a content addressable memory

MEMORY SYSTEM WITH REDUNDANT RAM MEMORY CELLS HAVING A DIFFERENT DE...

Fuse cell array with redundancy features

Semiconductor memory device

Integrated circuit device and electronic instrument

Thin film magnetic memory device having redundant configuration

Integrated circuit memory devices having multi-bit normal memory c...