Method and Apparatus for Programming Nonvolatile Memory

Abstract

Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a nonvolatile memory array accessed by word lines, diffusion bit lines, and metal bit lines, which reduces or eliminates the program disturb effect.

FIG. 2 models the loading of the memory array to determine the current which can cause the program disturb effect.

FIG. 3 models the loading of the memory array to determine a current associated with the program disturb effect, reduced by a medium voltage on a bit line.

FIG. 4 models the loading of the memory array to determine a current associated with the program disturb effect, reduced by a medium voltage on another bit line.

FIG. 5 shows an example integrated circuit with a nonvolatile memory array and a state machine that reduces the program disturb effect.

FIGS. 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A. 10B, 11A, and 11B are voltage and current trace simulations the shows the reduced program disturb effect.

Claims

1. A method of programming an array of nonvolatile memory cells, comprising: responsive to an instruction to program a nonvolatile memory cell of the array, applying a voltage arrangement to bit lines of the array to program the nonvolatile memory cell, including: applying a first bit line voltage to a first bit line electrically connected to a first current-carrying terminal of a nonvolatile memory cell of the array;applying a second bit line voltage to a second bit line electrically connected to a second current-carrying terminal of the nonvolatile memory cell, wherein the first bit line voltage has a larger magnitude than the second bit line voltage; andapplying a third bit line voltage to a third bit line electrically connected to at least one nonvolatile memory cell on a second bit line side of the nonvolatile memory cell, wherein the third bit line voltage has a magnitude in between magnitudes of the first bit line voltage and the second bit line voltage.

2. The method of claim 1, wherein the third bit line voltage reduces a magnitude of current from the second bit line through any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell.

3. The method of claim 1, wherein the third bit line voltage limits a magnitude of current from the second bit line through any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell to less than one fifth of a magnitude of current through the nonvolatile memory cell.

4. The method of claim 1, wherein the third bit line voltage reduces a magnitude of drain-to-source voltage of any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell.

5. The method of claim 1, wherein the third bit line voltage limits a magnitude of drain-to-source voltage of any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell to less than one quarter of a magnitude of drain-to-source voltage of the nonvolatile memory cell.

6. The method of claim 1, wherein the third bit line voltage substantially prevents programming of any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell.

7. The method of claim 1, further comprising: providing the third bit line voltage from bit line circuitry reducing the first bit line voltage to the third bit line voltage.

8. The method of claim 1, further comprising: providing the third bit line voltage from a transistor reducing the first bit line voltage to the third bit line voltage via a clamp bias.

9. The method of claim 1, further comprising: in a separate programming operation to program a second nonvolatile memory cell electrically coupled to the third bit line, applying the first bit line voltage to the third bit line to program the second nonvolatile memory cell.

10. The method of claim 1, wherein said applying the third bit line voltage is performed, if the voltage arrangement fails to program the nonvolatile memory cell a predetermined number of times.

11. The method of claim 1, wherein said applying the third bit line voltage is performed, if the program instruction fails to program the nonvolatile memory cell a sufficient number of times to raise a magnitude of the second bit line side to at least about six volts.

12. A nonvolatile memory, comprising: an array of nonvolatile memory cells each including a first current-carrying terminal and a second current-carrying terminal;a plurality of bit lines electrically connected to the first current-carrying terminal and the second current-carrying terminal of the nonvolatile memory cells of the array, the plurality of bit lines including a first bit line, a second bit line, and a third bit line;logic coupled to the plurality of bit lines, said logic including code responsive to an instruction to program a nonvolatile memory cell of the array by applying a voltage arrangement to the plurality of bit lines to program the nonvolatile memory cell, the voltage arrangement including: a first bit line voltage applied to the first bit line electrically connected to the first current-carrying terminal of the nonvolatile memory cell of the array;a second bit line voltage applied to the second bit line electrically connected to the second current-carrying terminal of the nonvolatile memory cell, wherein the first bit line voltage has a larger magnitude than the second bit line voltage; anda third bit line voltage applied to the third bit line electrically connected to at least one nonvolatile memory cell on a second bit line side of the nonvolatile memory cell, wherein the third bit line voltage has a magnitude in between magnitudes of the first bit line voltage and the second bit line voltage.

13. The memory of claim 12, wherein the third bit line voltage reduces a magnitude of current from the second bit line through any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell.

14. The memory of claim 12, wherein the third bit line voltage limits a magnitude of current from the second bit line through any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell to less than one fifth of a magnitude of current through the nonvolatile memory cell.

15. The memory of claim 12, wherein the third bit line voltage reduces a magnitude of drain-to-source voltage of any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell.

16. The memory of claim 12, wherein the third bit line voltage limits a magnitude of drain-to-source voltage of any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell to less than one quarter of a magnitude of drain-to-source voltage of the nonvolatile memory cell.

17. The memory of claim 12, wherein the third bit line voltage substantially prevents programming of any nonvolatile memory cells on the second bit line side of the nonvolatile memory cell.

18. The memory of claim 12, further comprising: bit line circuitry reducing the first bit line voltage to provide the third bit line voltage.

19. The memory of claim 12, further comprising: a transistor reducing the first bit line voltage via a clamp bias to provide the third bit line voltage.

20. The memory of claim 12, wherein the logic is responsive to a separate programming operation to program a second nonvolatile memory cell electrically coupled to the third bit line, by applying the first bit line voltage to the third bit line to program the second nonvolatile memory cell.

21. The memory of claim 12, wherein the logic applies the third bit line voltage, if the voltage arrangement fails to program the nonvolatile memory cell a predetermined number of times.

22. The memory of claim 12, wherein the logic applies the third bit line voltage, if the program instruction fails to program the nonvolatile memory cell a sufficient number of times to raise a magnitude of the second bit line side to at least about six volts.

23. The memory of claim 12, further comprising: a first pass transistor permitting the first bit line voltage to reach the first bit line; anda second pass transistor permitting the second bit line to reach the second bit line,wherein a same select signal turns on the first pass transistor and the second pass transistor.

24. A nonvolatile memory, comprising: an array means of nonvolatile memory cell means each including a first current-carrying terminal and a second current-carrying terminal;a plurality of bit line means electrically connected to the first current-carrying terminal and the second current-carrying terminal of the nonvolatile memory cell means of the array means, the plurality of bit line means including a first bit line means, a second bit line means, and a third bit line means;logic means coupled to the plurality of bit line means, said logic means including code responsive to an instruction to program a nonvolatile memory cell means of the array means by applying a voltage arrangement to the plurality of bit line means to program the nonvolatile memory cell means, the voltage arrangement including: a first bit line voltage applied to the first bit line means electrically connected to the first current-carrying terminal of the nonvolatile memory cell means of the array means;a second bit line voltage applied to the second bit line means electrically connected to the second current-carrying terminal of the nonvolatile memory cell means, wherein the first bit line voltage has a larger magnitude than the second bit line voltage; anda third bit line voltage applied to the third bit line means electrically connected to at least one nonvolatile memory cell on a second bit line means side of the nonvolatile memory cell means, wherein the third bit line voltage has a magnitude in between magnitudes of the first bit line voltage and the second bit line voltage.