Patent Application
20080016421
Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
In the following description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration the specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized because structural changes may be made without departing from the scope of the present invention.
The present invention provides a method and apparatus for providing programmable control of built-in self test. The programmable BIST controller is implemented to execute selected BIST operations, wherein software may choose to either enable or disable running of a particular BIST operation.
Depending upon the complexity of ASIC 100 and the need or desire to test functional cores 130, 140, 150, memory 120 and/or microprocessor core 110, BIST controllers 180-184 may be provided within the SOC during the chip's design. To perform a built-in self test, a host or an external controller 170 will instruct one of the BIST controllers 180-184 to supply a series of patterns to an applicable port of one of the cores 110, 120, 130, 140, 150 that is to be tested. These patterns are referred to as test algorithms. The operation of BIST controllers 180-184 involves exercising the functional cores 130, 140, 150, memory 120 and/or microprocessor core 110 according to their function, and after a period of time, determining whether the tested functional cores 130, 140, 150, memory 120 and/or microprocessor core 110 operated in an intended manner and with intended functionality.
The BIST techniques can be divided into categories. The two most common are logic BIST (LBIST), which is used to test at-speed the logic in the devices, and array BIST (ABIST), which is used to provide at-speed testing of the embedded arrays (i.e., RAMs). In the case wherein BIST circuitry 200 is a logic BIST engine, BIST control section 210 would thus instruct the pattern generator 210 to generate all necessary waveforms for repeatedly loading pseudorandom patterns into scan chains for the logic to be tested 240. The BIST control section 210 would then initiate a functional cycle (capture cycle) and log the captured responses. This test cycle is typically repeated many times with the results of each test cycle being combined in some manner with the results of the previous test cycles. The accumulated responses would be provided in a code known as a signature. The pattern comparison 230 would compare the signature to an expected signature to determine whether the logic to be tested 240 operated properly. Any corruption in the final signature at the end of the test indicates a defect in the chip.
In the case wherein BIST circuitry 200 is an Array BIST (ABIST) engine for testing the physical and logical structure of a memory array, the BIST control section 210 provides for bit-line stress testing, other case specific read-write combinations, data retention tests, etc. For the ABIST test, a BIST control section 210 is based on a programmable-state machine that is used to cause the pattern generation to algorithmically generate a variety of memory test sequences. As with LBIST, test patterns can be applied to the logic to be tested 240 at cycle speeds. Because of the regular structure of arrays, an ABIST engine can be shared among several arrays. This not only reduces the overhead per array, but also allows for decreased test times, since the arrays can be tested in parallel.
Functional cores may include a wide variety of functional elements such as peripheral cores, memory controllers, DMA engines, bus components, etc. One important type of functional core is a SERializer/DESerializer (SERDES) core. As networking architectures move forward, SERializer/DESerializer (SERDES) used in high speed communications to convert data from/to a serial data stream and a parallel data stream are being pushed to their maximum capabilities. Designers are being pushed to build more complex chips that handle increasingly fast data transmission rates. Thus, BIST circuitry 200 for testing functional cores, such as SERDES cores, makes it possible to develop higher speed products in shorter periods.
A SERDES design consists of a transmit data path, a receive data path, and a common block. In addition to these blocks a SERDES chip will usually have additional control logic and testability blocks to enhance test and characterization. Because the performance of a SERDES design often exceeds the performance of equipment needed to test it, BIST circuitry 200 needs to be included in the SERDES chip to ensure its testability.
Thus, a BIST circuit 200 may be provided into a functional core to verify the operation of the core. BIST functions in the form of pattern generation 220 and a corresponding pattern comparison 230 may be provided to test a function core such as a SERDES. For example, in the BIST mode, instead of the normal data inputs, a Serializer takes the parallel data from the BIST pattern generation 210 to generate the serial outputs. The pattern comparison 230 in the De-serializer checks the received data against an expected pattern to determine if there is any bit error. A SERDES can test itself by looping back the pattern from the Serializer to the De-serializer.
Besides the patterns, the BIST function can also include other data patterns that could provide additional diagnostic functions to what a SERDES has to offer. For example, the BIST pattern generator can generate the compliance pattern, defined in the PCI Express specifications, to make system-level diagnosis easier. By generating a constant 1's or 0's by the BIST pattern generation 220, DC level testing on the serial outputs can be easily performed
However, it is desirable to simply select which BIST tests to run rather than providing a BIST controller all of the control inputs. Further, it may be necessary or desirable to only run the BIST on selected ports of the complex circuit. Nevertheless, as described above with reference to
The programmable BIST controller 390, according to instructions 392 and input form external controller 370, initiates only BIST operations specified in the input from the external controller 370. The results are collected by the programmable BIST controller 390 for later processing. For example, the programmable BIST controller 390 may implement the specific interface protocols to run BIST on a High-Speed Serial Deserializer (HSS) core and further have the flexibility to enable or disable running the BIST operation to cores selected from the multiple cores 310, 320, 330, 340, 350 on the ASIC 300.
The foregoing description of the embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not with this detailed description, but rather by the claims appended hereto.
