Patent Application
20080285367
I. Field
The present disclosure relates generally to electronics, and more specifically to techniques for reducing leakage current in memory arrays.
II. Background
Integrated circuit (IC) fabrication technology continually improves and, as a result, the size of transistors continues to shrink. This enables more transistors and more complicated circuits to be fabricated on an IC die or, alternatively, a smaller die to be used for a given circuit. Smaller transistor size also supports faster operating speed and provides other benefits.
For complementary metal oxide semiconductor (CMOS) technology, which is widely used for digital circuits and some analog circuits, a major issue with shrinking transistor size is leakage current. Smaller transistor geometry results in higher electric field (E-field), which stresses a transistor and causes oxide breakdown. To decrease the E-field, a lower power supply voltage is often used for smaller geometry transistors. Unfortunately, the lower power supply voltage also increases the delay of the transistors, which is undesirable for high-speed circuits. To reduce the delay and improve operating speed, the threshold voltage (Vt) of the transistors is reduced. The threshold voltage is the voltage at which the transistors turn on. However, the lower threshold voltage and smaller transistor geometry result in higher leakage current, which is the current passing through a transistor when it is turned off.
Leakage current is more problematic as CMOS technology scales smaller. This is because leakage current increases at a high rate with respect to the decrease in transistor size. Furthermore, leakage current is a major issue for portable devices such as cellular phones, personal digital assistants (PDAs), laptop computers, etc. Leakage current consumes battery power and reduces standby time for portable devices that use batteries.
Reducing leakage current without sacrificing too much performance is a major challenge in CMOS designs, especially as IC technology scales smaller. Leakage current reduction is especially challenging for memory arrays, which are commonly used in many electronics devices. A memory array has many rows and many columns of memory cells to store data and may have many leakage current paths. Each leakage current path should be addressed in order to achieve low leakage current for the memory array.
Techniques for reducing leakage current in memory arrays are described herein. A memory array comprises multiple rows and multiple columns of memory cells. Bit lines are coupled to the columns of memory cells, and word lines are coupled to the rows of memory cells. The bit lines have disconnected paths to a power supply and float during a sleep mode for the memory array. The bit lines may be floated by turning off all transistors coupled between the power supply and the bit lines.
The bit lines may be coupled to (i) precharge circuits used to precharge the bit lines to logic high prior to each read or write operation, (ii) pass transistors used to couple the bit lines to sense amplifiers for read operations, and (iii) pull-up transistors in drivers used to drive the bit lines for write operations. The precharge circuits, pass transistors, and pull-up transistors may all be turned off during the sleep mode. The word lines may be set to a predetermined logic level to disconnect the memory cells from the bit lines during the sleep mode. The memory cells may be disconnected from the power supply via at least one head switch during the sleep mode, e.g., if data retention by the memory cells is not needed.
Various aspects and features of the disclosure are described in further detail below.
Techniques for reducing leakage current in memory arrays are described herein. The memory arrays may be for random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), video RAM (VRAM), synchronous graphic RAM (SGRAM), read only memory (ROM), Flash memory, etc. The memory arrays may be part of stand-alone memory devices or may be embedded within other devices, e.g., processors.
Memory array 150 includes M rows and N columns of memory cells 152, where M and N may each be any value. A memory cell is a circuit that can store a data value and may be implemented with various circuit designs. The M rows of memory cells are selected via M word lines WL1 through WLM. The N columns of memory cells are coupled to N differential bit lines BLI and BLIb through BLN and BLNb.
Address latch 110 receives an address for a memory cell or a block of memory cells to be accessed and latches the address. Address decoder 120 receives the latched address and may generate a row address based on the received address. Address decoder 120 may then perform pre-decoding on the row address and provide pre-decoded signals that indicate a specific word line to activate or assert. Word line drivers 120 receive the pre-decoded signals and drive a specific word line, as indicated by the pre-decoded signals, so that the desired row of memory cells can be accessed.
I/O circuit 170 includes various circuits for reading data from memory cells 152 and writing data to the memory cells. For example, I/O circuit 170 includes a sense amplifier and a data output buffer for each differential bit line to read data from the memory cells coupled to that bit line. I/O circuit 170 further includes a data latch and data input drivers for each differential bit line to write data to the memory cells coupled to that bit line.
Control signal generator 160 receives an external clock signal CLK and generates control signals used to control the operation of memory device 100. For example, generator 160 may generate control signals used for read and write operations.
Memory device 100 may be fabricated with a deep sub-micron CMOS process. Leakage current for memory device 100 may come from the following sources:
Leakage current via the peripheral circuits may be mitigated in several manners. In one design, the peripheral circuits may be implemented with both (i) low-Vt transistors for sections where high performance is desired and (ii) high-Vt transistors for sections where low leakage current is desired and high performance is not needed. In another design, low-Vt transistors may be used for the peripheral circuits and high-Vt transistors may be used as foot switches to connect or disconnect the peripheral circuits to circuit ground. In a functional/operational mode, the foot switches may be turned on, and the peripheral circuits may operate in the normal manner. In a sleep mode, the foot switches may be turned off, and leakage current through the peripheral circuits may be limited by the leakage current through the foot switches. High-Vt transistors may be used for the foot switches to reduce leakage current via the peripheral circuits.
Leakage current via memory array 150 may also be mitigated in several manners. First, the power supply to the memory cells may be disconnected with head switches during the sleep mode, which may reduce leakage current through the memory cells. Second, leakage current through the memory cells via the bit lines may be reduced by floating the bit lines during the sleep mode, as described below.
In general, a head switch and/or a foot switch may be used for a given circuit to reduce leakage current. It may be desirable to use head switches for memory array 150 to improve performance. Pull-down strength is an important factor for read/write performance. Adding foot switches in series with pull-down transistors within the memory cells may affect pull-down strength and impact performance. Head switches may be used for the memory array in order to minimize impact to pull-down strength. It may be desirable to use foot switches for peripheral circuits since foot switches may be implemented with less IC die area than head switches. In general, head switches or foot switches or both may be used for memory array 150. Head switches or foot switches or both may also be used for peripheral circuits. For clarity, the following description assumes that head switches are used for memory array 150 and foot switches are used for peripheral circuits.
In the design shown in
In the design shown in
Precharge circuit 220 includes two precharge P-FETs 222a and 222b for lines BLx and BLxb, respectively, and an equalization P-FET 224. P-FETs 222a and 222b have their gates coupled together and to a Precharge signal, their sources coupled to the Vddx power supply, and their drains coupled to lines BLx and BLxb, respectively. P-FET 224 has its gate coupled to the Precharge signal, its source coupled to line BLx, and its drain coupled to line BLxb. One line (either BLx or BLxb) is at logic low and the other line (either BLxb or BLx) is at logic high prior to a precharge operation. P-FET 224 connects lines BLx and BLxb together during the precharge operation and allows both P-FETs 222a and 222b to pull up the line that is at logic low toward logic high.
Multiplexer 230 includes N-FETs 232a and 232b and P-FETs 234a and 234b. N-FETs 232a and 232b have their gates coupled together and to a write signal ZW, their drains coupled to lines BLx and BLxb, respectively, and their sources coupled to write circuit 240. P-FETs 234a and 234b have their gates coupled together and to a read signal ZR, their sources coupled to lines BLx and BLxb, respectively, and their drains coupled to read circuit 250.
For a write operation, the ZW signal is at logic high for certain duration, and N-FETs 232a and 232b are turned on and couple lines BLx and BLxb to write circuit 240. The ZR signal is at logic high for the entire write operation, and P-FETs 234a and 234b are turned off and isolate read circuit 250 from lines BLx and BLxb. Lines BLx and BLxb are initially precharged to logic high, and either line BLx or BLxb is thereafter pulled to logic low to write to memory cell 152. N-FETs 232a and 232b are better at passing logic low/zero than P-FETs.
For a read operation, the ZR signal is at logic low for certain duration, and P-FETs 234a and 234b are turned on and couple lines BLx and BLxb to read circuit 250. The ZW signal is at logic low for the entire read operation, and N-FETs 232a and 232b are turned off and isolate write circuit 240 from lines BLx and BLxb. Lines BLx and BLxb are initially precharged to the same high voltage and are thereafter pulled apart by the selected memory cell 152. P-FETs 234a and 234b are better at passing high voltage or logic one on either line BLx or BLxb than N-FETs.
Write circuit 240 includes drivers 242a and 242b for lines BLx and BLxb, respectively, write driver logic 248, and an N-FET 249 that is used as a foot switch. Each driver 242 includes a P-FET 244 coupled in a stacked configuration with an N-FET 246. N-FET 246a has its source coupled to a virtual ground Vssp, its gate receiving a control signal Vn1 from logic 248, and its drain coupled to the drain of P-FET 244a. P-FET 244a has its gate receiving a control signal Vp1 from logic 248 and its source coupled to the Vddx power supply. FETs 244b and 246b are coupled in the same manner as FETs 244a and 244b and receive control signals Vp2 and Vn2, respectively, from logic 248. The drains of FETs 244a and 246a are coupled to line BLx, and the drains of FETs 244b and 246b are coupled to line BLxb. N-FET 249 has its source coupled to circuit ground, its gate receiving an SLP2 signal, and its drain providing virtual ground Vssp. The SLP2 signal is at logic high during the functional mode and at logic low during the sleep mode, which is opposite of the SLP1 signal. N-FET 249 may be implemented with a high-Vt transistor to achieve low leakage current. Logic 248 receives the Din data and the SLP2 signal and generates the Vp1 and Vn1 signals for FETs 244a and 246a, respectively, and the Vp2 and Vn2 signals for FETs 244b and 246b, respectively.
Read circuit 250 includes a precharge circuit 252 and a sense amplifier (Amp) 254. Precharge circuit 252 precharges the inputs of sense amplifier 254 to logic high prior to each read operation. Precharge circuit 252 may be implemented with three P-FETs coupled in the same manner as precharge circuit 220. Sense amplifier 254 senses the voltage difference between lines BLx and BLxb and provides the detected logic value.
Control signal generator 160 may be coupled to a foot switch implemented with an N-FET 260. N-FET 260 has its source coupled to circuit ground, its gate receiving the SLP2 signal, and its drain providing virtual ground Vssp for generator 160. Generator 160 may generate various control signals such as the ZW signal for N-FETs 232a and 232b, the ZR signal for P-FETs 234a and 234b, a data input driver clock (WCLK) signal used for write operations, and a sense amplifier enable (SEN) signal used for read operations.
Control signal generator 160 may be turned on or off via the foot switch implemented with N-FET 260. During the sleep mode, N-FET 260 may be turned off, the virtual ground Vssp may float between the Vddx power supply and circuit ground, and the control signals from generator 160 may slowly rise toward the Vddx power supply. Consequently, circuits that rely on their control signals being at logic low to turn off may not receive the logic low during the sleep mode. For example, N-FETs 232a and 232b rely on the ZW signal being at logic low to turn off. Since the ZW signal may float between Vddx and circuit ground during the sleep mode, N-FETs 232a and 232b may float during the sleep mode.
As shown in
As also shown in
Table 1 lists actions to perform to float bit lines BLx and BLxb, for the design shown in
During the functional mode, P-FETs 222a, 222b and 224 within precharge circuit 220 are turned on prior to each read or write operation to precharge bit lines BLx and BLxb to logic high. A NAND gate 226 receives a PRE signal and the SLP2 signal and generates the Precharge signal for P-FETs 222a, 222b and 224. The PRE signal is at logic low for each read or write operation and is at logic high at other times. During the functional mode, the SLP2 signal is at logic high, and the Precharge signal is an inverted version of the PRE signal. During the sleep mode, the SLP2 signal is at logic low, the Precharge signal is at logic high, and P-FETs 222a, 222b and 224 are turned off by the logic high on the Precharge signal. Precharge circuit 220 is thus turned off by the Precharge signal during the sleep mode.
During the functional mode, P-FETs 234a and 234b within multiplexer 230 may be turned on for read operations and turned off for write operations. During the sleep mode, P-FETs 234a and 234b may be turned off by applying logic high on the ZR signal. Generator 160 may be able to generate logic high on the ZR signal, even when N-FET 260 is turned off in the sleep mode, since the Vddx power supply is available to generator 160. Since N-FETs 234a and 234b can be turned off during the sleep mode, it may not be necessary to turn off precharge circuit 252. Nevertheless, precharge circuit 252 may be turned off during the sleep mode to further reduce leakage current.
During the functional mode, N-FETs 232a and 232b within multiplexer 230 may be turned on for write operations and turned off for read operations. P-FETs 244a and 244b within write circuit 240 may be turned on during a precharge phase of a write cycle to pull lines BLx and BLxb to logic high. During a write phase of the write cycle, driver 242a drives line BLx to logic low or high depending on the Din value, and driver 242b drives line BLxb to logic high or low depending on the Din value. During the sleep mode, N-FETs 232a and 232b may float because logic low is not achievable for the ZW signal with N-FET 260 turned off. P-FETs 244a and 244b within write circuit 240 may be turned off during the sleep mode to ensure no leakage current path from drivers 242a and 242b via bit lines BLx and BLxb through memory cell 152. Logic 248 may be able to generate logic high on the Vp1 and Vp2 signals for P-FETs 244a and 244b, respectively, even when N-FET 249 is turned off in the sleep mode, since the Vddx power supply is available to logic 248.
In the design shown in
Inverters 312a and 312b store a data value via positive feedback. If memory cell 152 stores logic high (‘1’), node A is at logic high and node B is at logic low. If memory cell 152 stores logic low (‘0’), node A is at logic low and node B is at logic high. For a memory read, lines BLx and BLxb are initially precharged to logic high by precharge circuit 220, then word line WLm is asserted to logic high, and N-FETs 318a and 318b are turned on. If memory cell 152 stores logic high, then line BLx is charged by inverter 312a via N-FET 318a, and line BLxb is discharged by inverter 312b via N-FET 318b. The converse is true if memory cell 152 stores logic low.
For a memory write, lines BLx and BLxb are initially precharged to logic high by precharge circuit 220, then word line WLm is asserted to logic high, and N-FETs 318a and 318b are turned on. To write logic high (‘1’) to memory cell 152, line BLx is driven high and forces node A to logic high via N-FET 318a, and line BLxb is driven low and forces node B to logic low via N-FET 318b. The converse is true when writing logic low to memory cell 152.
During the sleep mode, P-FET 210 may be turned off, and the Vddc supply voltage may then drop to an intermediate voltage determined by the leakage current through P-FET 210 and the leakage current through all memory cells coupled to P-FET 210. Inverters 312a and 312b may be isolated from bit lines BLx and BLxb by bringing word line WLm to logic low, which would then turn off N-FETs 318a and 318b.
I/O circuit 170b includes precharge circuit 220, multiplexer 230, write circuit 240, and read circuit 250 for each bit line. Write circuit 240 includes drivers 242a and 242b for lines BLx and BLxb, respectively, write driver logic 248, and N-FET 249. Within logic 248, an inverter 340 receives the Din data and provides an inverted Din. A NAND gate 342a receives the output of inverter 340 and the WCLK signal at two inputs and provides a latched Din. A NAND gate 342b receives the Din data and the WCLK signal at two inputs and provides a latched inverted Din. A NAND gate 344a receives the output of NAND gate 342a and the SLP2 signal at two inputs and provides the Vp1 signal for P-FET 244a. An inverter 346a receives the output of NAND gate 342a and provides the Vn1 signal for N-FET 246a. A NAND gate 344b receives the output of NAND gate 342b and the SLP2 signal at two inputs and provides the Vp2 signal for P-FET 244b. An inverter 346b receives the output of NAND gate 342b and provides the Vn2 signal for N-FET 246b.
During the functional mode, the SLP2 signal is at logic high, NAND gate 342a provides the latched Din, NAND gate 344a turns on P-FET 244a to pull up line BLx if Din is logic high, and inverter 346a turned on N-FET 246a to pull down line BLx if Din is logic low. NAND gate 342b provides the latched inverted Din, NAND gate 344b turns on P-FET 244b to pull up line BLxb if Din is logic low, and inverter 346b turned on N-FET 246b to pull down line BLxb if Din is logic high. During the sleep mode, the SLP2 signal is at logic low, the Vp1 signal from NAND gate 344a is at logic high, and P-FET 244a is turned off. The Vp2 signal from NAND gate 344b is also at logic high, and P-FET 244b is also turned off. NAND gates 344a and 344b thus turn off P-FETs 244a and 244b during the sleep mode and enable P-FETs 244a and 244b to be turned on or off during the functional mode. N-FETs 246a and 246b, inverters 340, 346a and 346b, and NAND gates 342a, 342b, 344a and 344b are all coupled to virtual ground Vssp from N-FET 249 and thus float during the sleep mode.
In one design, precharge circuit 220 may be coupled to the Vddx power supply directly, e.g., as shown in
In one design, N-FETs 234a and 234b within multiplexer 230 are turned off during the sleep mode, as described above. In another design, precharge circuit 252 may be turned off during the sleep mode, e.g., in the same manner as precharge circuit 220.
The FETs that are turned off during the sleep mode (e.g., P-FETs 222a, 222b and 224 within precharge circuit 220, P-FETs 234a and 234 within multiplexer 230, and P-FETs 244a and 244b within write circuit 240) may be implemented in a manner to reduce leakage current. For example, these FETs may be implemented with high-Vt transistors if fast operating speed is not required. Alternatively or additionally, these FETs may be implemented with longer lengths to reduce leakage current.
At least one head switch coupled between the power supply and the memory array and/or at least one foot switch coupled between the memory array and circuit ground may be turned off during the sleep mode (block 512). A plurality of precharge circuits for the plurality of bit lines may be turned off during the sleep mode (block 514). A plurality of pass transistors (e.g., P-FETs 234a and 234b) used to couple the plurality of bit lines to a plurality of sense amplifiers for read operations may be turned off during the sleep mode (block 516). Pull-up transistors (e.g., P-FETs 244a and 244b) in a plurality of drivers, which are used to drive the plurality of bit lines for write operations, may also be turned off during the sleep mode (block 518). The word lines may be set to a predetermined logic level (e.g., logic low) to disconnect the memory cells from the plurality of bit lines during the sleep mode (block 520).
One or more control circuits or logics (e.g., generator 160, NAND gate 226, and logic 248) may be used to generate control signals for the precharge circuits, the pass transistors for read operations, and the pull-up transistors for write operations. The control circuits or logics may be coupled to circuit ground via one or more foot switches and may provide logic high for the control signals during the sleep mode.
The techniques and memory arrays described herein may be used for various applications such as wireless communication, computing, networking, personal electronics, etc. The memory arrays may be implemented in stand-alone memory devices or embedded within processors, digital signal processors (DSPs), reduced instruction set computer (RISC) processors, advanced RISC machine (ARM) processors, graphics processors, graphics processing units (GPUs), controllers, microprocessors, etc. An exemplary use of the memory arrays for a wireless communication device is described below.
Wireless device 600 is capable of providing bi-directional communication via a receive path and a transmit path. On the receive path, signals transmitted by base stations are received by an antenna 612 and provided to a receiver (RCVR) 614. Receiver 614 conditions and digitizes the received signal and provides samples to a digital section 620 for further processing. On the transmit path, a transmitter (TMTR) 616 receives data to be transmitted from digital section 620, processes and conditions the data, and generates a modulated signal, which is transmitted via antenna 612 to the base stations.
Digital section 620 includes various processing, interface, and memory units such as, for example, a modem processor 622, a video processor 624, a controller/processor 626, a display processor 628, an ARM/DSP 632, a graphics processor 634, an internal memory 636, and an external bus interface (EBI) 638. Modem processor 622 performs processing for data transmission and reception, e.g., encoding, modulation, demodulation, and decoding. Video processor 624 performs processing on video content (e.g., still images, moving videos, and moving texts) for video applications such as camcorder, video playback, and video conferencing. Controller/processor 626 may direct the operation of various units within digital section 620. Display processor 628 performs processing to facilitate the display of videos, graphics, and texts on a display unit 630. ARM/DSP 632 may perform various types of processing for wireless device 600. Graphics processor 634 performs graphics processing, e.g., for graphics, video games, etc. Internal memory 636 stores data and/or instructions for various units within digital section 620. EBI 638 facilitates transfer of data between digital section 620 (e.g., internal memory 636) and a main memory 640.
Each of processors 622 through 634 may include an embedded memory, which may be implemented as described above. Internal memory 636 and main memory 640 may also be implemented as described above. Digital section 620 may be implemented with one or more application specific integrated circuits (ASICs) and/or some other type of ICs.
The techniques and memory arrays described herein may be implemented in various hardware units such as a memory IC, an ASIC, a DSP, a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a processor, and other electronic devices. The hardware units may be fabricated in various IC process technologies such as CMOS, N-MOS, P-MOS, bipolar-CMOS (Bi-CMOS), bipolar, etc. CMOS technology can fabricate both N-FETs and P-FETs on the same IC die, whereas N-MOS technology can only fabricate N-FETs and P-MOS technology can only fabricate P-FETs. The hardware units may be fabricated with any device size technology, e.g., 130 nanometer (nm), 90 nm, 65 nm, 30 nm, etc.
An apparatus implementing the techniques described herein may be a stand-alone unit or may be part of a device. The device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an ASIC such as a mobile station modem (MSM), (iv) a module that may be embedded within other devices, (v) a cellular phone, wireless device, handset, or mobile unit, (vi) etc.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
