Read-write (R-W) timing or clocking circuits Read-write (R-W) control signal generators or management

Industry

CPC
G11C7/22

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/22Read-write (R-W) timing or clocking circuits Read-write (R-W) control signal generators or management

Industries

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Patents Grantslast 30 patents

Information Patent Grant
System on chip and application processor
- Patent number 12,174,683
- Issue date Dec 24, 2024
- Samsung Electronics Co., Ltd.
- Junhee Yoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable memory timing
- Patent number 12,176,061
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods employing asynchronous FIFO buffer with read...
- Patent number 12,176,064
- Issue date Dec 24, 2024
- Advanced Micro Devices, Inc.
- Richard Martin Born
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input buffer circuit in semiconductor memory device having hysteres...
- Patent number 12,176,897
- Issue date Dec 24, 2024
- FIDELIX CO., LTD.
- Jae Jin Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Data receiving circuit, data receiving system, and memory device
- Patent number 12,176,055
- Issue date Dec 24, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Feng Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Channel routing for simultaneous switching outputs
- Patent number 12,176,065
- Issue date Dec 24, 2024
- ATI Technologies ULC
- Xuan Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer configurations for communications between memory dies and a...
- Patent number 12,170,127
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Sujeet V. Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Grant
Data receiving circuit, data receiving system and storage device
- Patent number 12,170,129
- Issue date Dec 17, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Feng Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for synchronization for an interconnection protocol, contro...
- Patent number 12,170,128
- Issue date Dec 17, 2024
- SK hynix Inc.
- Fu Hsiung Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing threshold voltage drift based on operating characteristics...
- Patent number 12,169,646
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Murong Lang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and circuits for slew-rate calibration
- Patent number 12,166,485
- Issue date Dec 10, 2024
- RAMBUS INC.
- Cosmin Iorga
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 12,165,731
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chien-Chen Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM non-clamping write driver with write assist
- Patent number 12,165,738
- Issue date Dec 10, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Data storage with improved cache read
- Patent number 12,165,735
- Issue date Dec 10, 2024
- SanDisk Technologies, Inc.
- Refael Ben-Rubi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for detecting margins of data signal and stora...
- Patent number 12,159,034
- Issue date Dec 3, 2024
- Huawei Technologies Co., Ltd.
- Yongyao Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock circuit, memory and method for manufacturing semiconductor st...
- Patent number 12,159,687
- Issue date Dec 3, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Meixiang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Channel and sub-channel throttling for memory controllers
- Patent number 12,154,657
- Issue date Nov 26, 2024
- Advanced Micro Devices, Inc.
- Kedarnath Balakrishnan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, method of operating the memory device, memory module...
- Patent number 12,154,651
- Issue date Nov 26, 2024
- Samsung Electronics Co., Ltd.
- Sunyoung Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data output control circuit and semiconductor device including the...
- Patent number 12,154,658
- Issue date Nov 26, 2024
- SK Hynix Inc.
- Kwang Soon Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method of controlling a memory chip
- Patent number 12,154,659
- Issue date Nov 26, 2024
- Kioxia Corporation
- Shinya Koizumi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory module architecture to support memory error cor...
- Patent number 12,153,827
- Issue date Nov 26, 2024
- George Pax
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution circuit and semiconductor apparatus including th...
- Patent number 12,147,264
- Issue date Nov 19, 2024
- SK hynix Inc.
- Ji Hyo Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency divider and memory device including the same
- Patent number 12,149,247
- Issue date Nov 19, 2024
- Samsung Electronics Co., Ltd.
- Jaewoo Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
High capacity memory system using standard controller component
- Patent number 12,148,462
- Issue date Nov 19, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Random data generation circuit and read/write training circuit
- Patent number 12,148,504
- Issue date Nov 19, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Biao Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices for multiple read operations
- Patent number 12,142,343
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for reducing DRAM power usage in performing read and wri...
- Patent number 12,142,344
- Issue date Nov 12, 2024
- NVIDIA Corporation
- Gautam Bhatia
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES AND METHODS FOR PARTIAL ARRAY SELF REFRESH MASKING
- Publication number 20240428841
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- YUKIMI MORIMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
HOST APPARATUS AND EXTENSION DEVICE
- Publication number 20240428843
- Publication date Dec 26, 2024
- KIOXIA Corporation
- Akihisa FUJIMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND CONTROL METHOD THEREFOR
- Publication number 20240428878
- Publication date Dec 26, 2024
- CXMT Corporation
- Zequn HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
STOP READ GO SETTINGS FOR LOW SUSPEND LATENCY APPLICATIONS
- Publication number 20240428834
- Publication date Dec 26, 2024
- Western Digital Technologies, Inc.
- Jing Fu
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING
- Publication number 20240428835
- Publication date Dec 26, 2024
- Rambus Inc.
- Andrew M. Fuller
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CLOCK CONTROL CIRCUIT AND METHOD FOR CONTROLLING MEMORY CLOCK
- Publication number 20240420749
- Publication date Dec 19, 2024
- Realtek Semiconductor Corp.
- WEI-CHEN LIU
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL ACCESS TO VOLATILE MEMORY BY A PROCESSING DEVICE FOR MACHI...
- Publication number 20240420742
- Publication date Dec 19, 2024
- Lodestar Licensing Group LLC
- Gil Golov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME
- Publication number 20240420754
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- DAE-SIK MOON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE REGIONS, AND ASSOCIATED DEVICES AND SYSTEMS
- Publication number 20240420747
- Publication date Dec 19, 2024
- Lodestar Licensing Group LLC
- KAZUHIRO YOSHIDA
- G11 - INFORMATION STORAGE
Information Patent Application
Low Power State Implementation in a Power Management Circuit
- Publication number 20240419237
- Publication date Dec 19, 2024
- Lodestar Licensing Group LLC
- Matthew David Rowley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE
- Publication number 20240412764
- Publication date Dec 12, 2024
- Samsung Electronics Co., Ltd.
- Jueon Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-BIT CELL AND MULTI-BIT CELL ARRAY INCLUDING THE SAME
- Publication number 20240412767
- Publication date Dec 12, 2024
- Samsung Electronics Co., LTD
- CHANHEE PARK
- G11 - INFORMATION STORAGE
Information Patent Application
Pre-Charger Circuit of Memory Device and Methods For Operating The...
- Publication number 20240412766
- Publication date Dec 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Masaya Hamada
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM PERFORMING HIERARCHICAL DUTY CYCLE ADJUSTER TRAINING...
- Publication number 20240404570
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- Ki-Seok PARK
- G11 - INFORMATION STORAGE
Information Patent Application
LOCAL INTERNAL DISCOVERY AND CONFIGURATION OF INDIVIDUALLY SELECTED...
- Publication number 20240403244
- Publication date Dec 5, 2024
- Rambus Inc.
- John Eric Linstadt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES
- Publication number 20240402788
- Publication date Dec 5, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK CONTROL CIRCUIT, MEMORY STORAGE DEVICE AND CLOCK CONTROL METHOD
- Publication number 20240402936
- Publication date Dec 5, 2024
- PHISON ELECTRONICS CORP.
- Cheng-Jui Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATION
- Publication number 20240404568
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Riccardo ZURLA
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST
- Publication number 20240404571
- Publication date Dec 5, 2024
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND MET...
- Publication number 20240404572
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- HYUNGJIN KIM
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND SYSTEMS FOR IMPROVING READ AND WRITE OF MEMORY CELLS
- Publication number 20240395297
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Ferdinando Bedeschi
- G11 - INFORMATION STORAGE
Information Patent Application
OFFSET CANCELLATION
- Publication number 20240395299
- Publication date Nov 28, 2024
- Lodestar Licensing Group LLC
- Martin Brox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE C...
- Publication number 20240395351
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Kyu Sung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
JITTER REDUCTION IN MIXED-SIGNAL PROCESSING CIRCUITS
- Publication number 20240395295
- Publication date Nov 28, 2024
- ADVANCED MICRO DEVICES, INC.
- Srikanth Reddy Gruddanti
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS
- Publication number 20240395296
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Hyun Seung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20240395298
- Publication date Nov 28, 2024
- Samsung Electronics Co., Ltd.
- BAEK JIN LIM
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL SKEW IN SOURCE-SYNCHRONOUS SYSTEM
- Publication number 20240395310
- Publication date Nov 28, 2024
- Rambus Inc.
- Shahram NIKOUKARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...
- Publication number 20240386928
- Publication date Nov 21, 2024
- Lodestar Licensing Group LLC
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME
- Publication number 20240386924
- Publication date Nov 21, 2024
- MICRON TECHNOLOGY, INC.
- THEODORE T. PEKNY
- G11 - INFORMATION STORAGE

Read-write (R-W) timing or clocking circuits Read-write (R-W) control signal generators or management

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

System on chip and application processor

Programmable memory timing

Apparatus and methods employing asynchronous FIFO buffer with read...

Input buffer circuit in semiconductor memory device having hysteres...

Data receiving circuit, data receiving system, and memory device

Channel routing for simultaneous switching outputs

Buffer configurations for communications between memory dies and a...

Data receiving circuit, data receiving system and storage device

Circuit for synchronization for an interconnection protocol, contro...

Managing threshold voltage drift based on operating characteristics...

Methods and circuits for slew-rate calibration

Memory device

SRAM non-clamping write driver with write assist

Data storage with improved cache read

Method and apparatus for detecting margins of data signal and stora...

Clock circuit, memory and method for manufacturing semiconductor st...

Channel and sub-channel throttling for memory controllers

Memory device, method of operating the memory device, memory module...

Data output control circuit and semiconductor device including the...

Memory system and method of controlling a memory chip

Non-volatile memory module architecture to support memory error cor...

Methods and apparatus for read-modify-write support in multi-banked...

Clock distribution circuit and semiconductor apparatus including th...

Frequency divider and memory device including the same

High capacity memory system using standard controller component

Random data generation circuit and read/write training circuit

Memory devices for multiple read operations

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Techniques for reducing DRAM power usage in performing read and wri...

Patents Applicationslast 30 patents

APPARATUSES AND METHODS FOR PARTIAL ARRAY SELF REFRESH MASKING

HOST APPARATUS AND EXTENSION DEVICE

MEMORY DEVICE AND CONTROL METHOD THEREFOR

STOP READ GO SETTINGS FOR LOW SUSPEND LATENCY APPLICATIONS

SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING

MEMORY CLOCK CONTROL CIRCUIT AND METHOD FOR CONTROLLING MEMORY CLOCK

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

PARALLEL ACCESS TO VOLATILE MEMORY BY A PROCESSING DEVICE FOR MACHI...

MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME

INTERFACE REGIONS, AND ASSOCIATED DEVICES AND SYSTEMS

Low Power State Implementation in a Power Management Circuit

RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE

MULTI-BIT CELL AND MULTI-BIT CELL ARRAY INCLUDING THE SAME

Pre-Charger Circuit of Memory Device and Methods For Operating The...

MEMORY SYSTEM PERFORMING HIERARCHICAL DUTY CYCLE ADJUSTER TRAINING...

LOCAL INTERNAL DISCOVERY AND CONFIGURATION OF INDIVIDUALLY SELECTED...

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

CLOCK CONTROL CIRCUIT, MEMORY STORAGE DEVICE AND CLOCK CONTROL METHOD

IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATION

LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST

APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND MET...

METHODS AND SYSTEMS FOR IMPROVING READ AND WRITE OF MEMORY CELLS

OFFSET CANCELLATION

SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE C...

JITTER REDUCTION IN MIXED-SIGNAL PROCESSING CIRCUITS

SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS

SEMICONDUCTOR DEVICE

SIGNAL SKEW IN SOURCE-SYNCHRONOUS SYSTEM

APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...

APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME