Read-write (R-W) timing or clocking circuits Read-write (R-W) control signal generators or management

Industry

CPC
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GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/22Read-write (R-W) timing or clocking circuits Read-write (R-W) control signal generators or management

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Signal generator for controlling timing of signal in memory device
- Patent number 12,211,586
- Issue date Jan 28, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Xiu-Li Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout for dual in-line memory to support 128-byte cache line proce...
- Patent number 12,211,577
- Issue date Jan 28, 2025
- Tachyum Ltd.
- Radoslav Danilak
- G11 - INFORMATION STORAGE
Information Patent Grant
Data-buffer controller/control-signal redriver
- Patent number 12,211,583
- Issue date Jan 28, 2025
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with tracking circuitry for reducing active power
- Patent number 12,211,587
- Issue date Jan 28, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Tsung-Hsien Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller, memory system and operating method of memory system
- Patent number 12,205,662
- Issue date Jan 21, 2025
- SK Hynix Inc.
- Young Ook Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipe latch circuit, operating method thereof, and semiconductor mem...
- Patent number 12,205,666
- Issue date Jan 21, 2025
- SK hynix Inc.
- Bo Kyeom Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Read data strobe path having variation compensation and delay lines
- Patent number 12,205,673
- Issue date Jan 21, 2025
- Cadence Design Systems, Inc.
- Hari Anand Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling memory requests with non-uniform latencies
- Patent number 12,204,754
- Issue date Jan 21, 2025
- Advanced Micro Devices, Inc.
- Kedarnath Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device related to calibrating a termination resistance
- Patent number 12,198,784
- Issue date Jan 14, 2025
- SK hynix Inc.
- Jung Taek You
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods including memory commands for semiconductor...
- Patent number 12,197,355
- Issue date Jan 14, 2025
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, memory device, and method for multi-phase clock training
- Patent number 12,198,783
- Issue date Jan 14, 2025
- Samsung Electronics Co., Ltd.
- Taegook Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory device and programming method thereof
- Patent number 12,198,764
- Issue date Jan 14, 2025
- Samsung Electronics Co., Ltd.
- Ji-Sang Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and memory system including the same
- Patent number 12,190,995
- Issue date Jan 7, 2025
- Samsung Electronics Co., Ltd.
- Byunghoon Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for outputting internal state of memory apparatus and mem...
- Patent number 12,189,976
- Issue date Jan 7, 2025
- Samsung Electronics Co., Ltd.
- Seong-hoon Woo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command-differentiated storage of internally and externally sourced...
- Patent number 12,189,523
- Issue date Jan 7, 2025
- RAMBUS INC.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command processing circuit and data processing circuit
- Patent number 12,190,992
- Issue date Jan 7, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liping Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Single port memory with multiple memory operations per clock cycle
- Patent number 12,190,994
- Issue date Jan 7, 2025
- Xilinx, Inc.
- Kumar Rahul
- G11 - INFORMATION STORAGE
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deferred fractional memory row activation
- Patent number 12,190,990
- Issue date Jan 7, 2025
- RAMBUS INC.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Information processing apparatus, information processing system, an...
- Patent number 12,183,384
- Issue date Dec 31, 2024
- Kioxia Corporation
- Akihisa Fujimoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device having an electrically floating body tr...
- Patent number 12,185,523
- Issue date Dec 31, 2024
- Zeno Semiconductor, Inc.
- Yuniarto Widjaja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatuses including temperature-based threshold voltage compensat...
- Patent number 12,183,416
- Issue date Dec 31, 2024
- Boon Hor Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared decoder circuit and method
- Patent number 12,183,432
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch circuit and memory device
- Patent number 12,184,285
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with compensated word line access delay
- Patent number 12,183,420
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Si Hong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for write clock double data rate duty cycle corre...
- Patent number 12,183,427
- Issue date Dec 31, 2024
- Cadence Design Systems, Inc.
- Sachin Ramesh Gugwad
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and method of operating the same
- Patent number 12,183,428
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Turbo mode SRAM for high performance
- Patent number 12,183,429
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company Limited
- Michael Clinton
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-Die Termination of Address and Command Signals
- Publication number 20250037746
- Publication date Jan 30, 2025
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY READOUT CIRCUIT
- Publication number 20250037745
- Publication date Jan 30, 2025
- INFINEON TECHNOLOGIES AG
- Mihail Jefremow
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20250037744
- Publication date Jan 30, 2025
- RENESAS ELECTRONICS CORPORATION
- Toshiki KIRYU
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SEN...
- Publication number 20250037747
- Publication date Jan 30, 2025
- Lodestar Licensing Group, LLC
- Troy A. Manning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE RELATED TO SIGNAL INTEGRITY OF CLOCK
- Publication number 20250029643
- Publication date Jan 23, 2025
- SK HYNIX INC.
- Choung Ki SONG
- G11 - INFORMATION STORAGE
Information Patent Application
Multibit High Density Read Only Memory Using Multiple Reference Biases
- Publication number 20250029669
- Publication date Jan 23, 2025
- Taalas Inc.
- Ljubisa Bajic
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES FOR MULTIPLE READ OPERATIONS
- Publication number 20250029641
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM
- Publication number 20250021260
- Publication date Jan 16, 2025
- KIOXIA Corporation
- Kensuke YAMAMOTO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuits And Methods For Generating Adjustable Signal Pulses That C...
- Publication number 20250022495
- Publication date Jan 16, 2025
- Altera Corporation
- Wee Leam Teoh
- G11 - INFORMATION STORAGE
Information Patent Application
DUTY CYCLE CORRECTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND...
- Publication number 20250023557
- Publication date Jan 16, 2025
- Samsung Electronics Co., Ltd.
- WOOSEUK OH
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME
- Publication number 20250021129
- Publication date Jan 16, 2025
- Samsung Electronics Co., Ltd.
- Kwanwoo NOH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...
- Publication number 20250022496
- Publication date Jan 16, 2025
- Lodestar Licensing Group LLC
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Application
LEAKAGE COMPENSATED DYNAMIC LATCH
- Publication number 20250006234
- Publication date Jan 2, 2025
- Intel Corporation
- Ganesan Iyer
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR PARTIAL ARRAY SELF REFRESH MASKING
- Publication number 20240428841
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- YUKIMI MORIMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
HOST APPARATUS AND EXTENSION DEVICE
- Publication number 20240428843
- Publication date Dec 26, 2024
- KIOXIA Corporation
- Akihisa FUJIMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND CONTROL METHOD THEREFOR
- Publication number 20240428878
- Publication date Dec 26, 2024
- CXMT Corporation
- Zequn HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
STOP READ GO SETTINGS FOR LOW SUSPEND LATENCY APPLICATIONS
- Publication number 20240428834
- Publication date Dec 26, 2024
- Western Digital Technologies, Inc.
- Jing Fu
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING
- Publication number 20240428835
- Publication date Dec 26, 2024
- Rambus Inc.
- Andrew M. Fuller
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CLOCK CONTROL CIRCUIT AND METHOD FOR CONTROLLING MEMORY CLOCK
- Publication number 20240420749
- Publication date Dec 19, 2024
- Realtek Semiconductor Corp.
- WEI-CHEN LIU
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL ACCESS TO VOLATILE MEMORY BY A PROCESSING DEVICE FOR MACHI...
- Publication number 20240420742
- Publication date Dec 19, 2024
- Lodestar Licensing Group LLC
- Gil Golov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME
- Publication number 20240420754
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- DAE-SIK MOON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE REGIONS, AND ASSOCIATED DEVICES AND SYSTEMS
- Publication number 20240420747
- Publication date Dec 19, 2024
- Lodestar Licensing Group LLC
- KAZUHIRO YOSHIDA
- G11 - INFORMATION STORAGE
Information Patent Application
Low Power State Implementation in a Power Management Circuit
- Publication number 20240419237
- Publication date Dec 19, 2024
- Lodestar Licensing Group LLC
- Matthew David Rowley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE
- Publication number 20240412764
- Publication date Dec 12, 2024
- Samsung Electronics Co., Ltd.
- Jueon Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-BIT CELL AND MULTI-BIT CELL ARRAY INCLUDING THE SAME
- Publication number 20240412767
- Publication date Dec 12, 2024
- Samsung Electronics Co., LTD
- CHANHEE PARK
- G11 - INFORMATION STORAGE
Information Patent Application
Pre-Charger Circuit of Memory Device and Methods For Operating The...
- Publication number 20240412766
- Publication date Dec 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Masaya Hamada
- G11 - INFORMATION STORAGE

Read-write (R-W) timing or clocking circuits Read-write (R-W) control signal generators or management

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Signal generator for controlling timing of signal in memory device

Aggressive write flush scheme for a victim cache

Layout for dual in-line memory to support 128-byte cache line proce...

Data-buffer controller/control-signal redriver

SRAM with tracking circuitry for reducing active power

Controller, memory system and operating method of memory system

Pipe latch circuit, operating method thereof, and semiconductor mem...

Read data strobe path having variation compensation and delay lines

Scheduling memory requests with non-uniform latencies

Semiconductor device related to calibrating a termination resistance

Methods and apparatus to reduce bank pressure using aggressive writ...

Apparatuses and methods including memory commands for semiconductor...

Apparatus, memory device, and method for multi-phase clock training

Non-volatile memory device and programming method thereof

Memory device and memory system including the same

Apparatus for outputting internal state of memory apparatus and mem...

Command-differentiated storage of internally and externally sourced...

Command processing circuit and data processing circuit

Single port memory with multiple memory operations per clock cycle

Fully pipelined read-modify-write support

Deferred fractional memory row activation

Information processing apparatus, information processing system, an...

Semiconductor memory device having an electrically floating body tr...

Apparatuses including temperature-based threshold voltage compensat...

Shared decoder circuit and method

Latch circuit and memory device

Memory array with compensated word line access delay

System and method for write clock double data rate duty cycle corre...

Memory circuit and method of operating the same

Turbo mode SRAM for high performance

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

On-Die Termination of Address and Command Signals

MEMORY READOUT CIRCUIT

SEMICONDUCTOR DEVICE

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SEN...

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

MEMORY MODULE RELATED TO SIGNAL INTEGRITY OF CLOCK

Multibit High Density Read Only Memory Using Multiple Reference Biases

MEMORY DEVICES FOR MULTIPLE READ OPERATIONS

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

MEMORY SYSTEM

Circuits And Methods For Generating Adjustable Signal Pulses That C...

DUTY CYCLE CORRECTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND...

STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME

APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...

LEAKAGE COMPENSATED DYNAMIC LATCH

APPARATUSES AND METHODS FOR PARTIAL ARRAY SELF REFRESH MASKING

HOST APPARATUS AND EXTENSION DEVICE

MEMORY DEVICE AND CONTROL METHOD THEREFOR

STOP READ GO SETTINGS FOR LOW SUSPEND LATENCY APPLICATIONS

SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING

MEMORY CLOCK CONTROL CIRCUIT AND METHOD FOR CONTROLLING MEMORY CLOCK

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

PARALLEL ACCESS TO VOLATILE MEMORY BY A PROCESSING DEVICE FOR MACHI...

MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME

INTERFACE REGIONS, AND ASSOCIATED DEVICES AND SYSTEMS

Low Power State Implementation in a Power Management Circuit

RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE

MULTI-BIT CELL AND MULTI-BIT CELL ARRAY INCLUDING THE SAME

Pre-Charger Circuit of Memory Device and Methods For Operating The...