Method and apparatus for repeat execution of delay analysis in circuit design

Information

  • Patent Application
  • 20070226669
  • Publication Number
    20070226669
  • Date Filed
    September 20, 2006
    18 years ago
  • Date Published
    September 27, 2007
    16 years ago
Abstract
An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.
Description

BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a schematic of hardware configuration of a delay analysis apparatus according to an embodiment of the present invention;



FIG. 2 is a schematic of a circuit element library;



FIG. 3 is a schematic of a wiring library;



FIG. 4 is a schematic of a target path to be modified;



FIG. 5 is a schematic of an analysis report;



FIG. 6 is a schematic of functional configuration of the delay analysis apparatus;



FIG. 7 is a schematic of slack probability distributions;



FIG. 8 is a schematic of an analysis report including modification directives;



FIG. 9 is a schematic of an analysis report including a result of a delay analysis of modified paths;



FIG. 10 is a schematic of a display example of the result of the delay analysis;



FIG. 11 is a flowchart of a processing performed by the delay analysis apparatus;



FIG. 12 is a flowchart of a generation of modification directive; and



FIG. 13 is a flowchart of an execution of statistical delay analysis.


Claims
  • 1. A computer-readable recording medium that stores therein a computer program for improving a delay of a target circuit, wherein the computer program causes a computer to execute: detecting a target path from among a plurality of paths in the target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path;extracting delay data of a second circuit component having an identical type to that of the first circuit component;determining whether to replace the first circuit component with the second circuit component based on the delay data of the first circuit component and the delay data of the second circuit component; andgenerating, when it is determined to replace the first circuit component with the second circuit component at the determining, a directive for replacing the first circuit component with the second circuit component.
  • 2. The computer-readable recording medium according to claim 1, wherein the computer program further causes the computer to execute: calculating a plurality of slack probability distributions of the paths based on the result of the delay analysis; andspecifying a reference path from among the paths based on the slack probability distributions, whereinthe detecting includes detecting, as the target path, a path of which slack probability distribution has a predetermined relationship to a slack probability distribution of the reference path.
  • 3. The computer-readable recording medium according to claim 1, wherein the computer program further causes the computer to execute: executing a delay analysis of the target circuit that includes the target path with the first circuit component being replaced with the second circuit component in accordance with the directive; andoutputting the result of the delay analysis along with the directive.
  • 4. The computer-readable recording medium according to claim 1, wherein the computer program causes the computer to execute the detecting, the extracting, the determining, and the generating repeatedly until a timing closure is achieved.
  • 5. A method of executing a delay analysis for improving a delay of a target circuit, comprising: detecting a target path from among a plurality of paths in the target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path;extracting delay data of a second circuit component having an identical type to that of the first circuit component;determining whether to replace the first circuit component with the second circuit component based on the delay data of the first circuit component and the delay data of the second circuit component; andgenerating, when it is determined to replace the first circuit component with the second circuit component at the determining, a directive for replacing the first circuit component with the second circuit component.
  • 6. The method according to claim 5, further comprising: calculating a plurality of slack probability distributions of the paths based on the result of the delay analysis; andspecifying a reference path from among the paths based on the slack probability distributions, whereinthe detecting includes detecting, as the target path, a path of which slack probability distribution has a predetermined relationship to a slack probability distribution of the reference path.
  • 7. The method according to claim 5, further comprising: executing a delay analysis of the target circuit that includes the target path with the first circuit component being replaced with the second circuit component in accordance with the directive; andoutputting the result of the delay analysis along with the directive.
  • 8. The method according to claim 5, wherein the detecting, the extracting, the determining, and the generating are repeated until a timing closure is achieved.
  • 9. An apparatus that executes a delay analysis for improving a delay of a target circuit, comprising: a detecting unit that detects a target path from among a plurality of paths in the target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path;an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component;a determining unit that determines whether to replace the first circuit component with the second circuit component based on the delay data of the first circuit component and the delay data of the second circuit component; anda generating unit that generates, when it is determined to replace the first circuit component with the second circuit component at the determining, a directive for replacing the first circuit component with the second circuit component.
  • 10. The apparatus according to claim 9, further comprising: a calculating unit that calculates a plurality of slack probability distributions of the paths based on the result of the delay analysis; anda specifying unit that specifies a reference path from among the paths based on the slack probability distributions, whereinthe detecting unit detects, as the target path, a path of which slack probability distribution has a predetermined relationship to a slack probability distribution of the reference path.
  • 11. The apparatus according to claim 9, further comprising: an executing unit that executes a delay analysis of the target circuit that includes the target path with the first circuit component being replaced with the second circuit component in accordance with the directive; andan outputting unit that outputs the result of the delay analysis along with the directive.
  • 12. The apparatus according to claim 9, wherein a series of processes performed by the detecting unit, the extracting unit, the determining unit, and the generating unit is repeated until a timing closure is achieved.
Priority Claims (1)
Number Date Country Kind
2006-081707 Mar 2006 JP national