BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of hardware configuration of a delay analysis apparatus according to an embodiment of the present invention;
FIG. 2 is a schematic of a circuit element library;
FIG. 3 is a schematic of a wiring library;
FIG. 4 is a schematic of a target path to be modified;
FIG. 5 is a schematic of an analysis report;
FIG. 6 is a schematic of functional configuration of the delay analysis apparatus;
FIG. 7 is a schematic of slack probability distributions;
FIG. 8 is a schematic of an analysis report including modification directives;
FIG. 9 is a schematic of an analysis report including a result of a delay analysis of modified paths;
FIG. 10 is a schematic of a display example of the result of the delay analysis;
FIG. 11 is a flowchart of a processing performed by the delay analysis apparatus;
FIG. 12 is a flowchart of a generation of modification directive; and
FIG. 13 is a flowchart of an execution of statistical delay analysis.