Number | Name | Date | Kind |
---|---|---|---|
5134616 | Barth, Jr. et al. | Jul 1992 | A |
5173906 | Dreibelbis et al. | Dec 1992 | A |
5313424 | Adams et al. | May 1994 | A |
5576999 | Kim et al. | Nov 1996 | A |
5631868 | Termullo, Jr. et al. | May 1997 | A |
5648934 | O'Toole | Jul 1997 | A |
5657284 | Beffa | Aug 1997 | A |
5706234 | Pilch, Jr. et al. | Jan 1998 | A |
5751647 | O'Toole | May 1998 | A |
5764574 | Nevill et al. | Jun 1998 | A |
5764650 | Debenham | Jun 1998 | A |
5781483 | Shore | Jul 1998 | A |
5781486 | Merritt | Jul 1998 | A |
5808351 | Nathan et al. | Sep 1998 | A |
5808947 | McClure | Sep 1998 | A |
5812466 | Lee et al. | Sep 1998 | A |
5835431 | Miner et al. | Nov 1998 | A |
5841709 | McClure | Nov 1998 | A |
5841712 | Wendell et al. | Nov 1998 | A |
5861660 | McClure | Jan 1999 | A |
5956350 | Irrinki et al. | Sep 1999 | A |
Entry |
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IBM Technical Disclosure Bulletin, “Semiconductor Memory Redundancy at the Module Level” vol. 23 No. 8 Jan. 1981, pp. 3601-3602. |
IBM Technical Disclosure Bulletin, “Efficient Use of Redundant Bit Lines for Yield Optimization”, vol. 31 No. 12 May 1989, pp. 107-108. |
IBM Technical Disclosure Bulletin, “Improved Computer Memory Chip”, vol. 39, No. 11 Nov. 1996, p. 51-52. |