Claims
- 1. A memory system comprising:
an array of memory cells, wherein each of the memory cells must be periodically refreshed to retain a data value; and a refresh control circuit that includes a temperature-adaptive oscillator for selecting a refresh period for refreshing the memory cells, wherein the temperature-adaptive oscillator is configured to select the refresh period in response to the subthreshold current of a reference transistor.
- 2. The memory system of claim 1, further comprising a capacitor element configured to be charged in response to the subthreshold current of the reference transistor.
- 3. The memory system of claim 2, further comprising an inverter chain coupled to the capacitor element, wherein the inverter chain is activated when a control voltage on the capacitor element exceeds a trip point of the inverter chain, and wherein the inverter chain provides a first refresh control signal used to control the refresh of the memory cells.
- 4. The memory system of claim 3, further comprising a reset transistor having a gate coupled to the inverter chain, a source coupled to ground and a drain coupled to the capacitor element, wherein the reset transistor is turned on after the inverter chain is activated, thereby discharging the capacitor element.
- 5. The memory system of claim 2, wherein the capacitor element comprises a p-channel MOS transistor having commonly connected source/drain regions.
- 6. The memory system of claim 1, further comprising a bias circuit coupled to the reference transistor, wherein the bias circuit is configured to cause the subthreshold current to flow through the reference transistor.
- 7. The memory system of claim 6, wherein the bias circuit comprises a first transistor and a second transistor, wherein the subthreshold current is a function of the width of the first transistor and the width of the second transistor.
- 8. The memory system of claim 1, wherein the reference transistor is of the same conductivity type as transistors used in the memory cells.
- 9. The memory system of claim 3, wherein the refresh control circuit further comprises a sequential logic element configured to receive the refresh control signal, and in response, activate a refresh request signal when the refresh control signal is activated.
- 10. The memory system of claim 9, wherein the sequential logic element is coupled to receive a second refresh control signal that indicates that the refresh operation has been performed, wherein the sequential logic element is configured to deactivate the refresh request signal in response to the second refresh control signal.
- 11. The memory system of claim 10, wherein the refresh control circuit includes a counter which is incremented in response to the activated or deactivated refresh request signal, the counter providing a refresh address that identifies a subset of the memory cells to be refreshed.
- 12. The memory system of claim 1, further comprising a constant transconductance current source for biasing the reference transistor.
- 13. A method of operating a memory system, the method comprising:
periodically activating a refresh control signal in response to a subtrheshold current through a reference transistor, wherein the subthreshold current varies with temperature; and refreshing an array of memory cells in response to the refresh control signal, wherein each of the memory cells must be periodically refreshed to retain a data value.
- 14. The method of claim 13, wherein the step of periodically activating the refresh control signal comprises charging a capacitor element with the subthreshold current.
- 15. The method of claim 14, further comprising activating the refresh control signal when the capacitor element is charged to a voltage greater than a trip point voltage.
- 16. The method of claim 15, further comprising:
introducing a delay to the activated refresh control signal, thereby creating a delayed activated refresh control signal; and discharging the capacitor element in response to the delayed activated refresh control signal.
- 17. The method of claim 15, further comprising deactivating the refresh control signal when the capacitor element is discharged to a voltage less than a trip point voltage.
- 18. The method of claim 13, further comprising setting a sequential logic element in response to the activated refresh control signal, whereby the sequential logic element activates a refresh request signal.
- 19. The method of claim 18, further comprising performing a refresh access to a subset of the memory cells in response to the activated refresh request signal.
- 20. The method of claim 19, further comprising:
operating the memory system in response to a clock signal; and enabling N external accesses and one refresh access to be consecutively performed during N cycles of the clock signal, wherein N is an integer equal to two or more.
- 21. The method of claim 19, further comprising activating a second refresh control signal when the subset of the memory cells is refreshed.
- 22. The method of claim 21, further comprising resetting the sequential logic element in response to the activated second refresh control signal, whereby the sequential logic element deactivates the refresh request signal.
- 23. The method of claim 22, further comprising modifying a refresh address counter in response to the deactivated refresh request signal.
RELATED APPLICATIONS
[0001] The present application is a continuation-in-part of U.S. patent application Ser. No. 10/114,282, by Wingyu Leung and Jae-Kwang Sim, entitled “METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING MULTIPLE CLOCK DIVISION” filed Apr. 3, 2002, which is a continuation-in-part of U.S. patent application Ser. No. 09/846,093, by Wingyu Leung, entitled “Method And Apparatus For Completely Hiding Refresh Operations In A DRAM Device Using Clock Division” filed Apr. 30, 2001, which is a continuation-in-part of U.S. patent application Ser. No. 09/405,607, by Wingyu Leung, entitled “Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same” filed Sep. 24, 1999, which is a continuation-in-part of U.S. Pat. No. 5,999,474, by Wingyu Leung and Fu-Chieh Hsu, entitled “Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory” issued Dec. 7, 1999.
[0002] The present application is further related to U.S. Pat. No. 6,028,804, by Wingyu Leung, entitled “Method and Apparatus for 1-T SRAM Compatible Memory” and issued Feb. 22, 2000; U.S. Pat. No. 6,222,785, by Wingyu Leung, entitled “Method and Apparatus For Refreshing A Semiconductor Memory Using Idle Memory Cycles”.issued Apr. 24, 2001; and U.S. Pat. No. 6,075,740, by Wingyu Leung, entitled “Method and Apparatus for Increasing The Time Available for Refresh For 1-T SRAM Compatible Devices”, issued Jun. 13, 2000. These patents are hereby incorporated by reference.
Continuation in Parts (4)
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Number |
Date |
Country |
Parent |
10114282 |
Apr 2002 |
US |
Child |
10300427 |
Nov 2002 |
US |
Parent |
09846093 |
Apr 2001 |
US |
Child |
10114282 |
Apr 2002 |
US |
Parent |
09405607 |
Sep 1999 |
US |
Child |
09846093 |
Apr 2001 |
US |
Parent |
09165228 |
Oct 1998 |
US |
Child |
09405607 |
Sep 1999 |
US |