Patent Application
20050253616
During manufacture, circuit assemblies (e.g., printed circuit boards and Multi-Chip Modules) need to be tested for interconnect defects such as open solder joints, broken connectors, and bent or misaligned leads (e.g., pins, balls, or spring contacts). One way to test for such defects is via capacitive lead-frame testing.
Positioned above the IC package 102 is a capacitive lead-frame test assembly 116. The exemplary test assembly 116 shown comprises a sense plate 118, a ground plane 120, and a buffer 122. The test assembly is coupled to an alternating current (AC) detector 124. A first, grounded test probe, TP_1, is coupled to lead 110 of the IC package. A second test probe, TP_2, is coupled to lead 108 of the IC package. The second test probe is also coupled to an AC source 126.
Additional and more detailed explanations of capacitive lead-frame testing are found in U.S. Pat. No. 5,557,209 of Crook et al. entitled “Identification of Pin-Open Faults by Capacitive Coupling Through the Integrated Circuit Package”, and in U.S. Pat. No. 5,498,964 of Kerschner entitled “Capacitive Electrode System for Detecting Open Solder Joints in Printed Circuit Assemblies”.
Over the years, various factors have interfered with the success of capacitive lead-frame testing. One factor is a lack of capacitive coupling between an IC lead-frame and a tester's sense plate. This problem is largely traced to the on-going miniaturization of IC packages and their lead-frames, as well as the imposition of ground shield and heat sinks between lead-frames and the sensor plate (some of which are internal to an IC's package). The miniaturization of lead-frames is also exacerbated by “area connection” packages. In an area connection package, the package's lead-frame is laid out as an array on a surface of the package, rather than in rows along the edges of the package. Examples of package area connections include ball grid arrays (BGAs; a lead-frame comprising a plurality of solder balls on a surface of a package) and land grid arrays (LGAs; a lead-frame comprising a plurality of stenciled or screened contact pads on a surface of a package). Area connection packages can be advantageous in that they often minimize the lengths of signal traces coupling a package's IC to its lead-frame. However, they can also interfere with capacitive lead-frame testing in that they sometimes make it difficult to position the sense plate of a capacitive lead-frame tester in close enough proximity to their lead-frames, they may have heat sinks or shielding between the IC and any external test probe.
One way to address some of the problems of IC miniaturization is disclosed in U.S. Pat. No. 6,087,842 and 6,097,203 of Parker et al. entitled “Integrated or Intrapackage Capability for Testing Electrical Continuity Between an Integrated Circuit and Other Circuitry”. These patents teach the placement of a capacitive sensor interior to an IC package, as illustrated in
The package assembly may include a grounded shield 210 or a heat sink 212. A capacitive probe 214 is included inside the package assembly. Probe 214 may be a ring or rectangular strip, near but not touching the bond wires 204 or the lead frame. The probe may have separate external electrical coupling 216 (ohmic or capacitive) for either a signal source or measurement circuitry, as shown in
One drawback to the internal test probe design of
There is a need for an internal test probe structure that overcomes the shortcomings of the prior art, without adding additional layers to the package.
A device enabling testing continuities of electrical paths through an area array integrated circuit on a circuit assembly is presented. The device may comprise a measurement access target contact on the area array package. Fill metal within one or more layers of the area array package may be connected to the measurement access target contact.
A method for testing continuity of electrical paths through an area array integrated circuit on a circuit assembly is presented. The method may comprise stimulating one or more nodes of the circuit assembly, coupling a test probe with a measurement access target contact on the area array package that is connected to the fill metal of the signal routing layers of the area array package, measuring an electrical characteristic of the area array package on the circuit assembly with a tester coupled to the test probe to determine continuity of electrical paths through the area array on the circuit assembly.
A more complete appreciation of this invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
FIGS. 4A-D illustrate top views of various signal routing layers of an exemplary area array package;
FIGS. 5A-D illustrate side cut-away views of the signal routing layers of an exemplary area array package as shown in FIGS. 4A-D;
A typical area array package is made from a collection of laminated circuit layers as depicted in FIGS. 4A-D and FIGS. 5A-D. The layers 300-306 serve as a plane to route signal traces 308-314 from the IC die bonding bumps 316 on a very small pitch grid to much larger ball-grid array of solder balls 328 on the bottom of the package. The layers 300-306 may have vertical connections implemented with vias 318-324, to route signals between planes. The signal routing layers shown in FIGS. 4A-D and 5A-D are “logical” and do not show implementation detail.
Area Array packages also contain power and ground distribution planes that also serve to create controlled impedance environments for signals, and reduce outside interference. Power and ground planes will often shield any capacitive coupling from the signal traces to a capacitive sensor placed over the top of the package, reducing or eliminating the ability to test for open solder joints or missing solder balls. The ground and power planes between these signal planes are not shown in FIGS. 4A-D and 5A-D.
Between any signal trace metal 312 and via pad 322 and the fill metal 330, there will be a small capacitance. This capacitance will vary with the parameters of the traces and fill metal. For example, the trace and fill metal height will affect capacitance, as well as separation. The wider the separation, the lower the capacitance. The run-length of traces 312 alongside fill metal 330 will affect capacitance. The longer the run-length, the higher the capacitance. The dielectric constant of the insulating and laminating materials (not shown) of the layers (300-306) will also affect the capacitance between the fill metal 330 and the traces and vias. The fill metal to trace and via capacitance can be calculated from these characteristics.
Extra vias 332 are used to connect the fill metal 330 of layers together electrically, as shown in
This offers another opportunity to add capacitive coupling as well. Via height, width, separation and the layer dielectric constant all determine the capacitance between trace vias 322 and fill metal vias 332.
Capacitances that can be created between fill metal and signal traces will be quite small, usually well into the femtoFarad ranges. A practical target value that can be used for measuring open solder connections would be in the 10-20 femtoFarad range for each signal to fill metal.
A measurement access target 350 is located on the top plane 352. Measurement access target 350 may be used to enable ohmic contact or capacitive coupling with a test probe. The test probe as shown in
Many integrated circuits will not have an exposed top surface due to the need to fill the top layer with an epoxy mixture to form a protective layer over the die. In such a case, the measurement access target 350 may be capacitively coupled to the sense plate 118 when it is brought in close proximity with it. The capacitance from the sense plate 118 to the measurement access target 350 should be significantly larger (e.g., 10×) than the larger capacitors between the fill metal 300 and the signal traces 308-314 of the area array package. This will prevent attenuation of the sensed signals.
Circuit designers may be concerned about the deliberate addition of capacitance between signals if they were to become larger than this. For example, if a die with several outputs and an input coupled capacitively to fill metal, the small capacitance to the input limits the additive effects of parallel outputs, even though many outputs could be pumping signal energy into the fill metal in parallel. Also, the fill metal has a substantially larger capacitance to the ground and power planes above and below it. This will divide and shunt most of the feedback signal away and minimize deleterious effects on circuit performance. However, this factor argues for keeping capacitive coupling to fill metal in lower (femtoFarad) ranges.
Positioned above the IC package 370 is a capacitive test probe 116. The exemplary test probe 116 shown may comprise a sense plate 118, a ground plane 120, and a buffer 122, as shown in
The capacitive test probe 116 is capacitively coupled to measurement access target 350 on the top layer 352 of the area array package 370. The measurement access target 350 is connected to the fill metal 330 of signal routing layers 300-306 by fill metal contact vias 332. The fill metal 330 of the signal routing layers 300-306 is capacitively coupled to the signal traces 308-314 of the signal routing layers 300-306. Note that the area array package 370 in
In operation, the test set-up of
After preparing the circuit assembly 100 for test, one or more nodes (Tp_2) of the circuit assembly 100 are stimulated (e.g., via an AC signal source 126), while other nodes TP_1 of the circuit may be grounded (to reduce noise and extraneous signal pickup). If the area array is in good condition and solder ball 508 is properly connected to the circuit assembly 100, then the capacitance detected should be equal to a predetermined capacitance (C)±a predetermined error (ε). If the solder ball 508 is open or the area array is faulty, then a different capacitance will be detected. If this difference in capacitance is detectable by the capacitive test probe and detector and it is greater than ε, than it can be used to determine if an open exists in the electrical path between the printed circuit board and the area array at solder ball 508. A test of the circuit assembly 100 may continue with sequential stimulation of the nodes under the circuit assembly associated with each solder ball connection between the circuit assembly 100 and the area array package 370.
While particular embodiments have been disclosed herein to illustrate and teach the invention, other embodiments are also anticipated. For example, while the vias 332 connecting the fill metal of the signal routing layers are shown substantially lined up, this is by no means the only embodiment and the vias 332 could be more than one between layers and could be placed wherever the vias make sense within the design rules of the signal routing layers. While the measured electrical characteristic disclosed was capacitance, for purposes of illustration, other electrical characteristics may be measured, such as inductance. Also, the electrical continuity of more than one area array package on a circuit assembly may be tested simultaneously using the teachings of the present invention. All of the above testing scenarios are within the scope of these teachings and anticipated by the inventor.
Although this preferred embodiment of the present invention has been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention, resulting in equivalent embodiments that remain within the scope of the appended claims. The appended claims are intended to be construed to include such variations, except as limited by the prior art.
