Patent Application
20130188410
The present disclosure relates generally to one-time programmable (OTP) storage elements. More specifically, the present disclosure relates to testing arrays of OTP storage elements.
Detection of manufacturing faults in storage elements generally involves electrical tests to store and retrieve data from these elements. Storage devices that include one-time programmable (OTP) storage elements are meant to be programmed by an end user after production tests, when they have already been incorporated in a system or device. In OTP storage elements, the programmed data is not erasable or reprogrammable. Rather OTP programming events are an irreversible destructive process. Because certain fields of OTP storage elements must remain un-programmed and dedicated for programming by a user, it has been difficult or virtually impossible to fully test one-time programmable arrays during production testing. Leaving portions of OTP storage devices untested has resulted, in an increased risk of test escapes.
An OTP array is programmed in order to test portions of read, paths such as bitlines and sense-amplifiers. However, programming the OTP elements involves relatively high voltages and currents that may cause side effects including the creation of faults by damaging program paths and read paths. The read paths cannot be independently tested if there are defects in the program controller or program logic. Present testing techniques do not provide a method to test the read paths independently without programming the OTP array.
One aspect of the present disclosure includes a method of testing an array of one-time programmable (OTP) devices. The method includes programming a first portion of a row of non-volatile memory (NVM) devices with test data and programming a first portion of a column of NVM devices with test data. The method also includes testing the row and column based on the programming of the first portions of the row and column. After a successful test, a remainder of the column and row are programmed with actual data.
Another aspect of the present disclosure includes an OTP apparatus. The OTP apparatus has an array of OTP devices arranged in rows and columns. A first set of pre-programmed ROM devices is appended to at least one column of the array. A second set of pre-programmed ROM devices is appended to at least one row of the array. The pre-programmed ROM devices store a predetermined test pattern for the array.
Another aspect of the present disclosure includes an apparatus for testing an array of OTP devices. The apparatus includes means for programming a first portion of a row of non-volatile memory (NVM) devices with test data and means for programming a first portion of a column of NVM devices with test data. The apparatus also includes means for testing the row and column based on the programming of the first portions of the row and column and means for programming a remainder of the column and row with actual data, after a successful test.
This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described, below. It should, be appreciated by those skilled, in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identity correspondingly throughout.
A first aspect of the present disclosure provides sacrificial cells to enable full testing of OTP arrays. Rows and columns are added that have sacrificial cells, which can be used for full testing of one-time programmable arrays. For this aspect, any number of sacrificial rows and sacrificial columns can be appended, to the array to ensure full testability. By writing data to the sacrificial rows and columns, testing of read functionality can be accomplished. That is, the data written to the sacrificial rows and columns is read during testing operations. Moreover, by confirming the OTP cells are properly written, the write functionality is also tested.
One aspect of the disclosure is described with reference to
The multiplexing function reduces or minimizes the number of macro outputs by allowing both sacrificial columns and non-sacrificial columns to share one output through the multiplexing circuitry 308. In other words, the multiplexing circuitry 308 enables a designer to maintain the same number of outputs after introducing the sacrificial columns. The multiplexer control signals labeled “SEL TSTWLBL” in
Other aspects of the present disclosure provide methods for designing OTP arrays for testability. The designs include sacrificial storage element fields strategically placed and programmed with various patterns or various read/write sequences to improve/maximize test coverage. Innumerable different patterns can be programmed in sacrificial rows and sacrificial columns of an OTP array according to the present disclosure.
Programming various patterns into sacrificial rows and sacrificial columns of an OTP array enables full testing of various functionalities of the OTP array. OTP array functionalities that may be tested by such patterns include programmability of the OTP cells, bitline functionality, wordline functionality, functionality of read sense-amplifiers, data out buffers and latches, program controller functionality, functionality of the program logic for programming the OTP ceils, and/or functionality of rows and row decoders, for example.
In addition to testing the functionality of OTP arrays, the configuration of sacrificial rows and sacrificial columns can provide a way to monitor the yield and reliability of the OTP cells. The configuration also enables the test set up to be verified.
The sacrificial rows and columns can be one time programmable (OTP) cells, as described above, or alternatively can be other types of non volatile memory, such as read only memory (ROM) ceils. Read-only memory (ROM) rows and ROM columns can be added to an OTP array to provide read testability of the OTP array. The number of ROM rows and ROM columns to be appended to the array should ensure full testability. ROM cells enable testing without programming of an OTP cell. Thus, the ROM rows and columns enable testing of read functionality regardless of whether write circuitry is fully operational.
In one configuration, according to an aspect of the present disclosure, the ROM rows 404 include at least two rows and the ROM columns 406 include at least two columns. A predetermined test pattern can include alternating ones and zeros, for example as seen in
A method of testing an array of one-time programmable (OTP) devices according to an aspect of the present disclosure is described with reference to
An apparatus for testing an array of one-time programmable (OTP) devices according to one aspect of the present disclosure includes means for programming a first portion of a row of NVM devices with test data and means for programming a first portion of a column of NVM devices with test data. The apparatus also includes means for testing the row and column based on the programming of the first portions of the row and column and means for programming a remainder of the column and row with actual data, after a successful test.
The programming means may be the bitlines, rows, row decoders, program controller, and/or programming logic. The means for testing a first portion of a row may be sacrificial columns 106, 206, 306, or ROM columns 406, and the means for testing a first portion of a column may be sacrificial rows 104, 204, 304, or ROM rows 404, for example. The means for programming the remainder of the column and row with actual data may include the non-sacrificial rows and columns of the OTP array 105, 205, 305, 405, for example. Although specific means have been set forth, it will be appreciated by those skilled in the art that not all of the disclosed means are required to practice the disclosed configurations. Moreover, certain well known means have not been described, to maintain focus on the disclosure.
In
Data recorded on the storage medium 704 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium 704 facilitates the design of the circuit design 710 or the semiconductor component 712 by decreasing the number of processes for designing semiconductor wafers.
Although specific circuitry has been set forth, it will be appreciated, by those skilled in the art that not all of the disclosed circuitry is required to practice the disclosed configurations. Moreover, certain well known circuits have not been described, to maintain focus on the disclosure.
For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored, in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used herein the term “memory” refers to types of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.
If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding configurations described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
The present application claims the benefit of U.S. Provisional Patent Application No. 61/588,753 to Uvieghara et al., filed on Jan. 20, 2012.
| Number | Date | Country | |
|---|---|---|---|
| 61588753 | Jan 2012 | US |
