Method and apparatus for verifying logic circuit

Abstract

A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments according to aspects of the invention with reference to the attached drawings, in which:

FIG. 1 is a block diagram showing the stages of designing a logic circuit using a prior art method;

FIG. 2 is a block diagram showing an embodiment of a logic circuit verification method according to aspects of the present invention;

FIG. 3 is a flowchart illustrating an embodiment of a logic circuit verification stage of FIG. 2; and

FIG. 4 is a table showing data resulting from the application of the conventional logic circuit verification method and the logic circuit verification method according to aspects of the present invention.

Claims

1. A logic circuit verification method, comprising: generating a wave file using a source file representing the logic circuit, the wave file including waveforms of each node of the logic circuit; andverifying the logic circuit using a design reference file and the wave file, the design reference file including ideal operations to be implemented for each node of the logic circuit.

2. The verification method of claim 1, wherein the generating of the wave file comprises: generating the source file; andoutputting information on waveforms of each node of the logic circuit that are included in the source file.

3. The verification method of claim 2, wherein the source file is one of HDL code, a gate-level net-list, and a SPICE net-list.

4. The verification method of claim 1, wherein the verifying of the logic circuit comprises comparing each of the nodes included in the design reference file with a corresponding node included in the wave file, and storing a result of the comparison in an apparatus for defect storage.

5. The verification method of claim 4, wherein the verifying of the logic circuit comprises: reading the design reference file;determining whether or not a node of the logic circuit from the design reference file corresponds to a node in the wave file;retrieving information on a waveform of the corresponding node from the wave file, when there the corresponding node exists in the wave file;determining the occurrence of a defect by comparing each node that has been retrieved from the design reference file with the corresponding node in the wave file;saving the defect in a storage device when the node that has been retrieved from the reference file does not correspond to a node in the wave file, or when a defect is found based on the result of the comparison;determining whether or not at least one node remains to be compared, when a defect is found and saved or no defect has been found based on the comparison result; andrepeating all the operations above when a node remains to be compared.

6. The verification method of claim 1, wherein the verifying of the logic circuit comprises verifying functional, timing, and analog characteristics of all of the nodes of the logic circuit.

7. The verification method of claim 6, wherein the verifying of the functional characteristics of a node in the logic circuit includes determining whether or not logical values at a predetermined point in time are within an allowed range specified by the design reference file,wherein the verifying of the timing characteristics of the node in the logic circuit includes determining whether or not a setup time, a hold time, and a propagation time of a signal are within allowed ranges specified by the design reference file, andwherein the verifying of the analog characteristics of the node in the logic circuit includes determining whether or not a duration time of the nodes' unknown state is within an allowed range specified by the design reference file.

8. The verification method of claim 1, wherein when the verifying of the logic circuit results in determining a defect in a design of the logic circuit, the method further comprises correcting the defect of the design in the logic circuit.

9. A logic circuit verification method, comprising: verifying functional, timing, and analog characteristics of each node of a logic circuit using waveforms resulting from a simulation of each node of the logic circuit and representations of ideal operations of each node of the logic circuit.

10. The method of claim 9, wherein the verifying includes determining if there is a waveform corresponding to each node in the logic circuit, the absence of a waveform indicating a defect.

11. The method of claim 9, wherein the waveforms are stored in a wave file and the ideal operations of each node are stored in a design reference file.

12. The method of claim 11, wherein the verifying comprises comparing information from the wave file with information from the design reference file.

13. An apparatus for verifying a logic circuit, configured to verify a logic circuit design by comparing waveform characteristics of each node of the logic circuit design with ideal operations of corresponding nodes of a logic circuit design.

14. The apparatus of claim 13, wherein the apparatus is configured to verify functional, timing, and analog signal characteristics of the logic circuit using the waveform characteristics of each node of the logic circuit.

15. The apparatus of claim 13, wherein the waveform characteristics are generated from a source file comprising one of HDL code, a gate-level net-list, and a SPICE net-list.

16. An apparatus for verifying a logic circuit design, comprising: a wave file generation stage configured to generate a source file representing the logic circuit design and to generate a wave file from the source file, the wave file comprising waveforms corresponding to nodes of the logic circuit design; anda logic circuit verification stage configured to verify the logic circuit design by comparing the waveforms corresponding to each of the nodes of the logic circuit design with a design reference file representing an ideal operation of each of the nodes of the logic circuit design.

17. The apparatus of claim 16, further comprising: a defect correction stage configured to correct defects in the logic circuit design detected during the verifying by the logic circuit verification stage.

18. The apparatus of claim 16, wherein the logic circuit verification stage is configured to verify functional, timing, and analog signal characteristics of the logic circuit design using waveform characteristics in the wave file for each node of the logic circuit design.

19. The apparatus of claim 16, wherein the logic circuit verification stage is configured to verify the logic circuit by comparing information in the wave file with information the reference design file.

20. The apparatus of claim 16, wherein the source file is one of HDL code, a gate-level net-list, and a SPICE net-list.