Claims
- 1. A method of inspecting a burn-in testing result of a plurality of dies, comprising:coupling an external power supply to at least one conductive pad disposed in an inactive region of a semiconductor wafer; and inspecting each of a plurality of burn-in indicating apparatuses, wherein each of said plurality of burn-in indicating apparatuses is coupled to a corresponding one die of a plurality of dies and is disposed on an active region of said semiconductor wafer, to determine whether a burn-in parameter has been satisfied.
- 2. A method according to claim 1, further comprising:discarding each single die of the plurality of dies in the event that the burn-in parameter has not been satisfied.
- 3. A method according to claim 1, further comprising:marking each single die of the plurality of dies with a visually perceptible indicia in the event that the burn-in parameter has not been satisfied.
- 4. A method according to claim 1, further comprising:retaining each single die of the plurality of dies with a visually perceptible indicia in the event that the burn-in parameter has been satisfied.
- 5. A method according to claim 1, further comprising:continuing with further testing or manufacturing operations for each single die of the plurality of dies that has satisfied the burn-in parameter.
- 6. A method according to claim 1, further comprising, in the event that less than half of the plurality of dies has satisfied the burn-in parameter; discarding said plurality of dies.
- 7. A method according to claim 1, wherein burn-in parameter comprises either:a die power-on timer for the period that the external power supply is coupled to each of the plurality of dies; or a period of time a circuit disposed on a one of the plurality of dies is operating.
- 8. A method according to claim 1, wherein the burn-in indicating apparatus comprises either; a one-bit counter adapted to switch when a pre-determined period of burn-in time has elapsed or a memory device adapted to record an aspect of the burn-in parameter.
- 9. A method according to claim 1, wherein said memory device comprises at least one fuse or a programmable memory device.
Parent Case Info
This application is a Div of Ser. No. 10/243,264 Sep. 16, 2002 U.S. Pat. No. 6,707,065 which is Div of Ser. No. 09/815,031 Mar. 22, 2001 U.S. Pat. No. 6,548,826 which is a CiP of Ser. No. 09/557,508 Apr. 25, 2000 U.S. Pat. No. 6,627,917.
US Referenced Citations (19)
Continuation in Parts (1)
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Number |
Date |
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Parent |
09/557508 |
Apr 2000 |
US |
Child |
09/815031 |
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US |