Claims
- 1. A field-programmable gate array (FPGA) comprising:an array of RAM memory cells comprising at least one row of RAM memory cells, each RAM cell of said at least one row of RAM memory cells coupled to a row driver line; a row decoder coupled to a first end of said row driver line of said each at least one row of RAM memory cells; a monitoring memory cell coupled to at least one of said row driver line; and wherein each said monitoring memory cell is also coupled to a memory writing line.
- 2. The FPGA of claim 1 wherein said each monitoring memory cell is coupled to a second end of each said row driver line.
- 3. The FPGA of claim 1 wherein said each monitoring memory cell is coupled to said at least one row driver line at each corner of said array of RAM memory cells.
- 4. In a FPGA having a plurality of RAM memory cells as the programming mechanism, the FPGA further having erase circuitry for clearing the RAM memory cells for reprogramming of the FPGA, a method for:providing at least one monitoring memory cell coupled to said erase circuitry; initiating a memory clear phase on said at least one monitoring memory cell; and making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a cleared monitoring memory cell.
- 5. The method of claim 4, further comprising:returning to said memory clear phase if the determination as to whether the output signal from each said monitoring memory cell indicates a cleared monitoring memory cell, indicates that at least one of each said monitoring memory cell was not cleared.
- 6. The method of claim 5, further comprising:issuing an alarm if the method returns to said memory clear phase more than a predetermined number of times.
- 7. In a FPGA having a plurality of RAM memory cells as the programming mechanism, a method for:providing at least one monitoring memory cell having write circuitry for verifying the writing function to said monitoring memory cell; initiating a memory write phase on said at least one monitoring memory cell; making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a properly memory written to monitoring memory cell.
- 8. The method of claim 7, further comprising:returning to said memory write phase if it is determined that the output signal from at least one monitoring memory cell indicates that it was not properly written to.
- 9. The method of claim 8, further comprising:issuing an alarm if the method returns to said memory write phase more than a predetermined number of times.
- 10. In a FPGA having a plurality of RAM memory cells as the programming mechanism, the FPGA further having erase circuitry for clearing the RAM memory cells for reprogramming of the FPGA, a method for:providing at least one monitoring memory cell coupled to said erase circuitry, said monitoring memory cell having write circuitry for verifying the writing function to said monitoring memory cell; initiating a memory clear phase on said at least one monitoring memory cell; making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a cleared monitoring memory cell; initiating a memory write phase on said at least one monitoring memory cell; making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a properly memory written to monitoring memory cell.
- 11. The method of claim 10, further comprising:returning to said memory clear phase if the determination, as to whether the output signal from each said monitoring memory cell indicates a cleared monitoring memory cell, indicates that each said monitoring memory cell was not cleared; and returning to said memory write phase if it is determined that the output signal from at least one monitoring memory cell indicates that it was not properly written to.
- 12. The method of claim 11, further comprising:issuing an alarm if the method returns to said memory clear phase more than a first predetermined number of times; and issuing an alarm if the method returns to said memory write phase more than a second predetermined number of times.
- 13. In a FPGA having a plurality of RAM memory cells as the programming mechanism, the FPGA further having erase circuitry for clearing the RAM memory cells for reprogramming of the FPGA, a method for:providing at least one monitoring memory cell coupled to said erase circuitry, said monitoring memory cell having write circuitry for verifying the writing function to said monitoring memory cell; initiating a first memory clear phase on said at least one monitoring memory cell; making a first determination as to whether the output signal from each said at least one monitoring memory cell indicates a cleared monitoring memory cell; initiating a memory write phase on said at least one monitoring memory cell; making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a memory written to monitoring memory cell; initiating a second memory clear phase on said at least one monitoring memory cell; and making a second determination as to whether the output signal from each said at least one monitoring memory cell indicates a cleared monitoring memory cell.
- 14. The method of claim 13, further comprising:returning to said first memory clear phase if the first determination, as to whether the output signal from each said monitoring memory cell indicates a cleared monitoring memory cell, indicates that each said monitoring memory cell was not cleared; returning to said memory write phase if it is determined that the output signal from at least one monitoring memory cell indicates that it was not properly written to; and returning to said second memory clear phase if the second determination, as to whether the output signal from each said monitoring memory cell indicates a cleared monitoring memory cell, indicates that each said monitoring memory cell was not cleared.
- 15. The method of claim 14, further comprising:issuing an alarm if the method returns to said first memory clear phase more than a first predetermined number of times; issuing an alarm if the method returns to said memory write phase more than a second predetermined number of times; and issuing an alarm if the method returns to said second memory clear phase more than a third predetermined number of times.
- 16. An FPGA capable of verifying the functioning of its RAM memory cells, comprising:means for providing at least one monitoring memory cell coupled to the FPGA erase circuitry; means for initiating a memory clear phase on said at least one monitoring memory cell; and means for making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a cleared monitoring memory cell.
- 17. The FPGA of claim 16, further comprising:means for returning to said memory clear phase if the determination as to whether the output signal from each said monitoring memory cell indicates a cleared monitoring memory cell, indicates that at least one of each said monitoring memory cell was not cleared.
- 18. The FPGA of claim 17, further comprising:means for issuing an alarm if the means for returning to said memory clear phase returns to said memory clear phase more than a predetermined number of times.
- 19. An FPGA capable of verifying the functioning of its RAM memory cells, comprising:means for providing at least one monitoring memory cell having write circuitry for verifying the writing function to said monitoring memory cell; means for initiating a memory write phase on said at least one monitoring memory cell; means for making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a properly memory written to monitoring memory cell.
- 20. The FPGA of claim 19, further comprising:means for returning to said memory write phase if it is determined that the output signal from at least one monitoring memory cell indicates that it was not properly written to.
- 21. The FPGA of claim 20, further comprising:means for issuing an alarm if the method returns to said memory write phase more than a predetermined number of times.
- 22. An FPGA capable of verifying the functioning of its RAM memory cells, comprising:means for providing at least one monitoring memory cell coupled to the FPGA's erase circuitry, said monitoring memory cell having write circuitry for verifying the writing function to said monitoring memory cell; means for initiating a memory clear phase on said at least one monitoring memory cell; means for making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a cleared monitoring memory cell; means for initiating a memory write phase on said at least one monitoring memory cell; and means for making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a properly memory written to monitoring memory cell.
- 23. The FPGA of claim 22, further comprising:means for returning to said memory clear phase if the determination, as to whether the output signal from each said monitoring memory cell indicates a cleared monitoring memory cell, indicates that each said monitoring memory cell was not cleared; and means for returning to said memory write phase if it is determined that the output signal from at least one monitoring memory cell indicates that it was not properly written to.
- 24. The FPGA of claim 23, further comprising:means for issuing an alarm if the method returns to said memory clear phase more than a first predetermined number of times; and means for issuing an alarm if the method returns to said memory write phase more than a second predetermined number of times.
- 25. An FPGA capable of verifying the functioning of its RAM memory cells, comprising:means for providing at least one monitoring memory cell coupled to the FPGA's erase circuitry, said monitoring memory cell having write circuitry for verifying the writing function to said monitoring memory cell; means for initiating a first memory clear phase on said at least one monitoring memory cell; means for making a first determination as to whether the output signal from each said at least one monitoring memory cell indicates a cleared monitoring memory cell; means for initiating a memory write phase on said at least one monitoring memory cell; means for making a determination as to whether the output signal from each said at least one monitoring memory cell indicates a memory written to monitoring memory cell; means for initiating a second memory clear phase on said at least one monitoring memory cell; and means for making a second determination as to whether the output signal from each said at least one monitoring memory cell indicates a cleared monitoring memory cell.
- 26. The FPGA of claim 25, further comprising:means for returning to said first memory clear phase if the first determination, as to whether the output signal from each said monitoring memory cell indicates a cleared monitoring memory cell, indicates that each said monitoring memory cell was not cleared; means for returning to said memory write phase if it is determined that the output signal from at least one monitoring memory cell indicates that it was not properly written to; and means for returning to said second memory clear phase if the second determination, as to whether the output signal from each said monitoring memory cell indicates a cleared monitoring memory cell, indicates that each said monitoring memory cell was not cleared.
- 27. The FPGA of claim 26, further comprising:means for issuing an alarm if the method returns to said first memory clear phase more than a first predetermined number of times; means for issuing an alarm if the method returns to said memory write phase more than a second predetermined number of times; and means for issuing an alarm if the method returns to said second memory clear phase more than a third predetermined number of times.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of application Ser. No. 09/654,240, filed on Sep. 2, 2000, now granted U.S. Pat. No. 6,476,636 on Nov. 5, 2002.
US Referenced Citations (14)
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
09/654240 |
Sep 2000 |
US |
Child |
10/077188 |
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US |