Patent Application
20080084359
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the drawings presented herein, in which:
The use of the same reference symbols in different drawings indicates similar or identical items.
The following description in combination with the Figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be interpreted as a limitation on the scope or applicability of the teachings.
The personal computer 102 preferably has an internal card with a GPU including logic and circuitry to control the settings of the display devices 106, 108, 110, and 112 and to receive configuration data from each of the display devices. The GPU is capable of independently controlling the resolution and refresh rate of the display devices. The internal card or some other output of the personal computer 102 has an electrical interface with the ability to drive a DisplayPort-enabled display with either one, two or four high speed wire pairs in addition to an auxiliary channel for Extended Display Identification Data (EDID) and audio transmissions. In particular, the auxiliary channel is used to establish control settings such as resolution and refresh rate with the display devices 106, 108, 110, and 112.
The video display controller 104 communicates between the personal computer 102 and the display devices 106, 108, 110, and 112. The video display controller 104 is preferably a multiplexing device external to the personal computer 102, and includes an input connector 114 for communicating over a line 116 with a digital-to-analog connector or DisplayPort transmit (DPTX) connector on the internal card in the personal computer 102. The video display controller 104 also has an auxiliary channel and/or EDID manager 118 and a lane splitter 120. The EDID manager 118 multiplexes the EDID/DDC channels by reading the EDID data from the multiple monitors in a serial fashion and combining it with an appropriate high speed wire pair such as main link (ML) 0 channel 122, ML1 channel 124, ML2 channel 126, or ML3 channel 128.
The lane splitter 120 communicates with display device connectors 130, 132, 134, and 136, which in turn respectively communicate with displays 106, 108, 110, and 112 through lines 138, 140, 142 and 144. The lane splitter 120 performs point-to-point separation of the four high speed pairs. It should be understood that while the EDID manager 118 and the lane splitter 120 are shown logically, their functions may be performed by a single processor. With this arrangement, one or more of the display devices 106, 108, 110 and 112 can normally be driven by a single high speed pair at a resolution in a range centered about 1280 by 1024 pixels at a refresh rate centered in a range of about 75 Hz. It should be appreciated that lower end (e.g., 6 and 8 bit) digital flat panel displays can be driven at higher resolution and/or refresh rates.
It should be noted that neither of the embodiments shown and described herein affects the functionality of the DisplayPort™ specification, such as the hot plug detect functionality. Although only a few exemplary embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the embodiments of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the embodiments of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.
