This application is related to a U.S. Patent Application entitled “CACHE LINE CONVERTER,” Ser. No. 09/650,101, filed on Aug. 25, 2000: a U.S. Patent Application entitled “DRAM MICROPROCESSOR CACHE WITH ON-CHIP TAGS,” Ser. No. 09/652,797, filed on Aug. 31, 2000; a U.S. Patent Application entitled “METHOD AND CACHE-COHERENCE SYSTEM ALLOWING PURGING OF MID-LEVEL CACHE ENTRIES WITHOUT PURGING LOWER-LEVEL CACHE ENTRIES,” Ser. No. 09/650,100, filed on Aug. 25, 2000: and a U.S Patent application entitled “MULTIPROCESSOR NODE CONTROLLER CIRCUIT AND METHOD,” Ser. No. 09/407,428, filed on Sep. 29, 1999, each incorporated herein by reference.
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