1. Field of the Invention
The invention relates to a method and circuit for optimizing bit line power consumption.
2. Description of Related Art
Static Random Access Memory (SRAM) is a type of semiconductor memory and widely applied to many electronic devices.
Referring to
EBL=PBL×t=CBL×ΔVBL×VCS (1)
Usually, the bit line capacitance is almost a constant, and ΔVBL can be also treated as a constant. In general, ΔVBL is about 100 mV. Therefore, one can concludes that the power (energy) consumption EBL can be decreased if the power voltage VCS is decreased.
However, in current advanced process, such as process for 40 nm, 28 nm or 14 nm, etc., ΔVBL will be varied with the process, voltage and temperature, etc. the voltage ΔVBL can not be treated as a constant. Therefore, there is a need of method or system for providing more precise simulation to optimize the bit line power consumption for such advanced process or others.
In view of above, a method and circuit for optimizing bit line power consumption is provided to efficiently and precisely optimize the bit line power consumption.
In one embodiment, a bit line power implementing circuit for memory cells having an average and a worst threshold voltages is provided. The bit line power implementing circuit comprises a bit line discharge oscillator, a decoder, a first and a second counters, a divider and a multiplier. The bit line discharge oscillator receives a supply voltage and converts the supply voltage to a pulse. The decoder is coupled to the bit line discharge oscillator to decode the pulse, and provides a first pulse with a first frequency and a second pulse with a second frequency. The first counter is coupled to the decoder, and receives the first pulse with the first frequency, and outputs a signal proportional to the average read current. The second counter is coupled to the decoder, and receives the first pulse with the first frequency, and outputs a signal proportional to the minimum read current. The divider is coupled to the first and the second counters, and outputs a read current ratio of the average read current to the minimum read current. The multiplier is coupled to the divider to multiply the supply voltage the read current ratio to output a bit line power consumption corresponding to the supply voltage.
In another embodiment, a bit line power optimizing circuit for memory cells having an average and a worst threshold voltages is further provided. In addition to the above bit line power implementing circuit, the optimizing circuit further comprises a power source, providing the supply voltage to the bit line discharge oscillator; a first register, coupled to the multiplier, for storing a previous bit line power consumption; a comparator, coupled to the multiplier and the first register, receiving a current bit line power consumption, for comparing the current and the previous bit line power consumptions, and outputting a comparison result; a second register, for storing the supply voltage; and an operating unit, coupled to the second register and the comparator, for receiving the comparison result and perform an operation on the supply voltage. When the current bit line power consumption is smaller than the previous bit line power consumption, the comparison result makes the operating unit to decreases the supply voltage by a preset amount, and provide the decreased supply voltage to the power source. When the current bit line power consumption is larger than the previous bit line power consumption the comparison result makes the operating unit to deactivate.
In one embodiment, the bit line discharge oscillator further comprises a logic unit; and a plurality of bit line discharge units, coupled to the logic unit, wherein the bit line discharge units are serially connected, an input of the first bit line discharge unit is coupled to an output of the logic unit and an output of the final bit line discharge unit is fedback to an input of the logic unit. In one embodiment, the logic unit comprises an XOR gate. In one embodiment, the first pulse corresponds to an average read current related to the average threshold voltage and the second pulse corresponds to the minimum read current related to the worst threshold voltage.
In one embodiment, the bit line discharge unit further comprises a memory cell having a word line and a bit line; a buffer, coupled between the word line and an input of the bit line discharge unit; an inverter, coupled between the bit line and an output of the bit line discharge unit; a transistor, coupled between the bit line and the input of the bit line discharge unit, for pre-charging the bit line; and a bit line load, coupled to the bit line.
In still another embodiment, a bit line power optimizing method for memory cells is provided. The method can be executed by a computing system. The method comprises steps of obtaining a word line turn-on time corresponding to a worst bit among the memory cells, wherein a minimum offset voltage is satisfied during the word line turn-on time; obtaining an average offset voltage based on the word line turn-on time, wherein the average offset voltage is a function of the supply voltage; obtaining a bit line power consumption from the average offset voltage and the supply voltage; plotting a diagram of the bit line power consumption versus and the supply voltage according to a condition of the manufacturing process; obtaining a target supply voltage at a reverse point where the bit line power consumption versus is minimum; and outputting the target supply voltage and obtaining an optimized power consumption corresponding to the target supply voltage.
In one embodiment, the average offset voltage can be further a function of the supply voltage and a threshold voltage. In addition, the condition of the manufacturing process can be temperature, threshold voltage or a combination thereof.
To make the above features and advantages of the disclosure more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
In the embodiment, a suitable mathematical model capable of simulating and optimizing the bit line (BL) power consumption for the advanced process or others is first derived and explained. Then, a corresponding method and a circuit or system are provided for implementing the power optimization scheme.
The read current Iread, BL capacitance CBL, WL turn-on time TWL and ΔVBL can be expressed as the following expression (2).
In the expression (2), if assuming the transistor serving as the passing gate is a MOS transistor, the current-voltage relationship can be expresses by k(VCS−Vth)2VCS. Then, the offset voltage ΔVBL can be further reformulated as follows.
Considering the worst bits, the worst bit usually has a corresponding minimum read current. Referring to
Using the relationship showing in the expression (3), a following expression (5) can be obtained by rearranging the expression (4), in which the threshold voltage for the worst bit is αVth.
k(VCS−αVth)2VCS×TWL=100CBL (5)
Then, considering the normal bits or the average BL swing (i.e., the typical value in the random variation shown in
Combing the expressions (5) and (6), the average offset voltage (BL swing) ΔVBL
In addition, from the expression (1), it can be concluded as following expression (8) that the bit line power consumption EBL is proportional to ΔVBL×VCS, in which the offset voltage ΔVBL is no longer a constant, but a variable.
EBL=CBL×ΔVBL×ΔVCS∝ΔVBL×VCS (8)
Then, combing the expressions (7) and (8), following expression (9) can be obtained.
From the expression (9), it can understand how the power consumption (energy) EBL of bit line is varied with the threshold voltage Vth and VCS. In the expression (9), the constant “100”, the supply voltage VCS and the coefficient α are dependent on the manufacturing process.
According to the expression (9), the power consumption EBL at different supply voltage VCS can be obtained. For example, the power consumptions EBL at a high supply voltage VCS1 and high supply voltage VCS2 can be represented respectively by following expressions (10) and (11).
Next, a method, a circuit or a system for implementing bit line power optimization is described in detail.
In step S102, an average offset voltage ΔVBL
In step S104, a bit line power consumption EBL is obtained from the average offset voltage ΔVBL
In step S106, a diagram of the bit line power consumption EBL versus and the supply voltage VCS is plotted according to a condition of the manufacturing process. Followings depict some examples of the plotted diagrams.
In step S108, a target supply voltage at a reverse point of where the bit line power consumption versus is minimum is obtained. Then, in step S110, the target supply voltage is outputted so as to obtain an optimized power consumption corresponding to the target supply voltage. For example, referring to
Next, a circuit for implementing the above method is described in details.
The first counter 118 and the second counter 120 are coupled to the output of decoder 116, and generates signals respectively proportional to the minimum read current Iread
Next, the detail operation of the BL power implementing circuit 110 is further described. In order to implementing bit line power consumption EBL by a circuit, the bit line power consumption EBL in the expression (9) is further rearranged to the following expression (12).
The term VCS−(α−1)Vth defined as VCSD, and the expression (12) is simplified as following expression (13).
Usually, the voltage VCSD is smaller than VCS, which can reflect the coefficient α. Generally, the voltage VCSD can be calculated by subtracting the supply voltage VCS with an amount that is obtained from a test key of a selected manufacturing process. This amount can be picked up from a look-up table or inputted by manually.
In addition, digital codes CVCS [N:0] and CVCSD [N:0] are further defined as following expressions (14) and (15).
CVCS[N:0]∝fVCS∝(VCS−Vth)2 (14)
CVCSD[N:0]∝fVCSD∝(VCSD−αVth)2 (15)
In this circuit as shown in
In operation, for example the BL discharge oscillator 112 generates a pulse with frequency fVCS. As the decoder 116 receives the pulse with frequency fVCS, the decoder 116 selects a route to the first counter 118 to count the pulse to generate the digital code CVCS [N:0]. Next, in order to generate the digital code CVCSD [N:0], a test mode signal is inputted to the decoder 116. Once receiving the test mode signal, the decoder 116 begins to receive the pulse with frequency fVCSD, the decoder 116 selects another route to the second counter 120 to count the pulse to generate the digital code CVCSD [N:0]. For example, the test mode signal can be a clock signal with a longer period, and the decoder 116 processes the pulse with frequency fVCS during the ON period and the pulse with frequency fVCSD during the OFF period.
After the first counter 118 counts the pulse with a frequency fVCS to generate a digital code CVCS [N:0] and second counter 120 counts the pulse with a frequency fVCSD to generate a digital code CVCSD [N:0], the divider 112 receives the digital code CVCS [N:0] and the digital code CVCSD [N:0] and then divides the digital code CVCS [N:0] by the digital code CVCSD [N:0] to generates a current ratio code Iratio [N:0]. Namely, the divider 112 outputs current ratio Iratio represented by the following expression (16).
Next, the multiplier 124 receives the current ratio Iratio and the supply voltage VCS, both of which are represented by current ratio code Iratio [N:0] and voltage code TM [N:0] (where TM [N:0] is proportional to VCS). Then, in the following expression (17), the multiplier 124 outputs a digital code PBL [N:0] that is proportional to the bit line power consumption EBL.
Therefore, according to the circuit shown in
As shown in
Following is a simulation result. As listed in TABLE 1, stages of the BL discharge units 112b can be set to be larger 21 because the variation can be smaller than ±10. The suitable stages of the BL discharge units 112b can be properly set according to the selected manufacturing process.
In operation, usually a maximum supply voltage VCS is first inputted to the BL power implementing circuit 110 to generate a corresponding digital code PBL [N:0]. This code is then provides to the first register 130 and the comparator 132. Then, the power source 100 further inputs a next supply voltage, for example, VCS−ΔV. Then the BL power implementing circuit 110 generates another digital code corresponding to the supply voltage VCS−ΔV. Then, the comparator 132 compares the current PBL[M:0] and the previous PBL_B [M:0], and then outputs the comparison result Vcomp.
If the result represents that the current PBL[M:0] is smaller than the previous PBL_B [M:0], it means the power consumption has a descending trend. Then, the comparison result Vcomp is provided to the adder 136 to further add an amount to decrease the supply voltage VCS. After the adder 136 provides the result to the power source 100, the power source 100 provides a next supply voltage, such as VCS−2ΔV to the BL power implementing circuit 110.
The aforementioned procedure is continuously executed until the current power consumption begins larger than the previous power consumption. When this condition is satisfied, it means that the supply voltage reaches a reverse point, and the power consumption reaches its minimum value. Therefore, the proposed optimizing circuit can obtain a optimized supply voltage, and thus find the optimized bit line power consumption.
In summary, according to the embodiment of the method or the circuit for optimizing bit line power consumption, the offset voltage ΔVBL is no longer a constant. The variation of e ΔVBL due to the advanced process or process difference can be truly and precisely reflected. A suitable optimized bit line power can be efficiently and precisely obtained.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this specification provided they fall within the scope of the following claims and their equivalents.
Number | Name | Date | Kind |
---|---|---|---|
3663828 | Low et al. | May 1972 | A |
3818402 | Golaski et al. | Jun 1974 | A |
4163944 | Chambers et al. | Aug 1979 | A |
4245355 | Pascoe et al. | Jan 1981 | A |
4409608 | Yoder | Oct 1983 | A |
4816784 | Rabjohn | Mar 1989 | A |
5159205 | Gorecki et al. | Oct 1992 | A |
5208725 | Akcasu | May 1993 | A |
5212653 | Tanaka | May 1993 | A |
5406447 | Miyazaki | Apr 1995 | A |
5446309 | Adachi et al. | Aug 1995 | A |
5583359 | Ng et al. | Dec 1996 | A |
5637900 | Ker et al. | Jun 1997 | A |
5760456 | Grzegorek et al. | Jun 1998 | A |
5808330 | Rostoker et al. | Sep 1998 | A |
5923225 | De Los Santos | Jul 1999 | A |
5959820 | Ker et al. | Sep 1999 | A |
6008102 | Alford et al. | Dec 1999 | A |
6081146 | Shiochi et al. | Jun 2000 | A |
6172378 | Hull et al. | Jan 2001 | B1 |
6194739 | Ivanov et al. | Feb 2001 | B1 |
6246271 | Takada et al. | Jun 2001 | B1 |
6285578 | Huang | Sep 2001 | B1 |
6291872 | Wang et al. | Sep 2001 | B1 |
6370372 | Molnar et al. | Apr 2002 | B1 |
6407412 | Iniewski et al. | Jun 2002 | B1 |
6427226 | Mallick et al. | Jul 2002 | B1 |
6448858 | Helms et al. | Sep 2002 | B1 |
6452442 | Laude | Sep 2002 | B1 |
6456221 | Low et al. | Sep 2002 | B2 |
6461914 | Roberts et al. | Oct 2002 | B1 |
6480137 | Kulkarni et al. | Nov 2002 | B2 |
6483188 | Yue et al. | Nov 2002 | B1 |
6486765 | Katayanagi | Nov 2002 | B1 |
6509805 | Ochiai | Jan 2003 | B2 |
6518165 | Yoon et al. | Feb 2003 | B1 |
6521939 | Yeo et al. | Feb 2003 | B1 |
6545547 | Fridi et al. | Apr 2003 | B2 |
6560306 | Duffy et al. | May 2003 | B1 |
6588002 | Lampaert et al. | Jul 2003 | B1 |
6593838 | Yue | Jul 2003 | B2 |
6603360 | Kim et al. | Aug 2003 | B2 |
6608363 | Fazelpour | Aug 2003 | B1 |
6611223 | Low et al. | Aug 2003 | B2 |
6625077 | Chen | Sep 2003 | B2 |
6630897 | Low et al. | Oct 2003 | B2 |
6639298 | Chaudhry et al. | Oct 2003 | B2 |
6653868 | Oodaira et al. | Nov 2003 | B2 |
6668358 | Friend et al. | Dec 2003 | B2 |
6700771 | Bhattacharyya | Mar 2004 | B2 |
6720608 | Lee | Apr 2004 | B2 |
6724677 | Su et al. | Apr 2004 | B1 |
6756656 | Lowther | Jun 2004 | B2 |
6795001 | Roza | Sep 2004 | B2 |
6796017 | Harding | Sep 2004 | B2 |
6798011 | Adan | Sep 2004 | B2 |
6810242 | Molnar et al. | Oct 2004 | B2 |
6822282 | Randazzo et al. | Nov 2004 | B2 |
6822312 | Sowlati et al. | Nov 2004 | B2 |
6833756 | Ranganathan | Dec 2004 | B2 |
6841847 | Sia et al. | Jan 2005 | B2 |
6847572 | Lee et al. | Jan 2005 | B2 |
6853272 | Hughes | Feb 2005 | B1 |
6876056 | Tilmans et al. | Apr 2005 | B2 |
6885534 | Ker et al. | Apr 2005 | B2 |
6901126 | Gu | May 2005 | B1 |
6905889 | Lowther | Jun 2005 | B2 |
6909149 | Russ et al. | Jun 2005 | B2 |
6927664 | Nakatani et al. | Aug 2005 | B2 |
6958522 | Clevenger et al. | Oct 2005 | B2 |
7009252 | Lin et al. | Mar 2006 | B2 |
7027276 | Chen | Apr 2006 | B2 |
7205612 | Cai et al. | Apr 2007 | B2 |
7262069 | Chung et al. | Aug 2007 | B2 |
7365627 | Yen et al. | Apr 2008 | B2 |
7368761 | Lai et al. | May 2008 | B1 |
7405642 | Hsu et al. | Jul 2008 | B1 |
7486586 | Fifield et al. | Feb 2009 | B2 |
7672100 | Van Camp | Mar 2010 | B2 |
20020019123 | Ma et al. | Feb 2002 | A1 |
20020036545 | Fridi et al. | Mar 2002 | A1 |
20020188920 | Lampaert et al. | Dec 2002 | A1 |
20030076636 | Ker et al. | Apr 2003 | A1 |
20030127691 | Yue et al. | Jul 2003 | A1 |
20030183403 | Kluge et al. | Oct 2003 | A1 |
20050068112 | Glenn | Mar 2005 | A1 |
20050068113 | Glenn | Mar 2005 | A1 |
20050087787 | Ando | Apr 2005 | A1 |
20060006431 | Jean et al. | Jan 2006 | A1 |
20060108694 | Hung et al. | May 2006 | A1 |
20060267102 | Cheng et al. | Nov 2006 | A1 |
20070102745 | Hsu et al. | May 2007 | A1 |
20070210416 | Hsu et al. | Sep 2007 | A1 |
20070234554 | Hung et al. | Oct 2007 | A1 |
20070246801 | Hung et al. | Oct 2007 | A1 |
20070249294 | Wu et al. | Oct 2007 | A1 |
20070296055 | Yen et al. | Dec 2007 | A1 |
20080094166 | Hsu et al. | Apr 2008 | A1 |
20080185679 | Hsu et al. | Aug 2008 | A1 |
20080189662 | Nandy et al. | Aug 2008 | A1 |
20080200132 | Hsu et al. | Aug 2008 | A1 |
20080299738 | Hsu et al. | Dec 2008 | A1 |
20080303623 | Hsu et al. | Dec 2008 | A1 |
20090029324 | Clark | Jan 2009 | A1 |
20090201625 | Liao et al. | Aug 2009 | A1 |
20100279484 | Wang et al. | Nov 2010 | A1 |
Entry |
---|
Tachibana et al., “A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit,” IEEE International Solid-State Circuits Conference, Feb. 20, 2013, pp. 320-321. |