Claims
- 1. A method of generating write control signals insensitive to glitches on a data input signal comprising the steps of:(A) enabling a write of a first or second value in response to a data input transition; (B) holding in a ready state until the data input is stable; and (C) writing stable data into a memory array.
- 2. The method according to claim 1, further comprising the step of:(D) enabling a write for an opposite polarity of said data input.
- 3. The method according to claim 1, further comprising the step of:receiving a first and a second signal.
- 4. The method according to claim 3, wherein said first and second signals comprise state signals.
- 5. The method according to claim 3, wherein steps (A), (B) and (C) respond to said first and second signals.
- 6. The method according to claim 5, wherein steps (A), (B) and (C) further respond to transitions of said first and second signals.
- 7. The method according to claim 1, further comprising the step of:receiving a global write signal.
- 8. The method according to claim 7, wherein step (C) further responds to said global write signal.
- 9. The method according to claim 3, wherein step (B) further comprises the step of:entering a feedback state.
- 10. The method according to claim 9, wherein step (B) further comprises the step of:entering said feedback state when said first and second signals are in a first predetermined state.
- 11. The circuit according to claim 10, wherein step (B) further comprises the step of:proceeding to said ready state after entering said feedback state.
- 12. The method according to claim 1, wherein step (B) comprises a plurality of ready states.
- 13. The method according to claim 1, wherein step (B) further comprises the step of:proceeding to said ready state in response to a transition of a global write signal.
- 14. The method according to claim 1, wherein step (A) further comprises ending a write pulse.
- 15. The method according to claim 1, wherein step (A) further comprises the step of:when said data input transitions, re-enabling a write of said first or second value.
- 16. The method according to claim 1, wherein said second value comprises an opposite polarity of said first value.
- 17. A method for controlling writing of data comprising the steps of:(A) receiving one or more signals; and (B) writing data in response to a data input, wherein said writing is insensitive to glitches on said data input.
- 18. The method according to claim 17, wherein step (B) further comprises waiting for a steady state of said data input.
- 19. A method for controlling writing of data comprising the steps of:(A) enabling a write of a value in response to a data input transition; and (B) writing said value into a memory array only when said data input becomes stable.
- 20. The method according to claim 19, wherein step (A) is further responsive to a first and a second state signal.
Parent Case Info
This is a divisional of U.S. Ser. No. 09/344,514, filed Jun. 25, 1999 now U.S. Pat. No. 6,101,134.
US Referenced Citations (10)
Foreign Referenced Citations (1)
Number |
Date |
Country |
404339267 |
Nov 1992 |
JP |