The present application relates to the technical field of solid state drive (SSD), and more particularly to a method and a device for marking dirty bits in an L2P table based on SSD.
At present, SSDs have been widely used in various occasions. Due to their excellent indicators in performance, power consumption, and environmental adaptability, they are gradually replacing traditional hard drives.
In the traditional L2P table management technology based on SSD, the dirty bit is 1 bit. When the 1-bit dirty bit is used, after the L2P table flush starts and before the flush completes the dirty clearing, if the dirty bit is 1, the 1 state will be cleared by the following dirty clearing, so the dirty state will be lost. The traditional solution is to avoid the dirty bit being 1 after the start of the L2P table flush and before the flush completes the dirty clearing. In order to do this, it is necessary to prohibit processing write commands within the range of this L2P table for a while, so that the write commands are blocked, which affects write performance.
One of the objects of embodiments of the present application is to provide a method and a device for marking dirty bits in an L2P table based on SSD, in order to solve the problem of prohibiting processing write commands within the range of this L2P table, such that the write commands are blocked, and write performance is affected.
In order to solve above technical problem, the present application adopts the technical scheme as following:
In a first aspect, a method for marking dirty bits in an L2P table based on a solid state drive is provided, which including:
obtaining a marking request of dirty bits in the L2P table based on the solid state drive;
broadening a corresponding dirty bit in the L2P table to 2 bits according to the request;
setting the dirty bit from a binary number 00 to a binary number 01 through a state machine when a first write command request is obtained;
setting the dirty bit from the binary number 01 to a binary number 10 through the state machine when flush operation starts; and
setting the dirty bit from the binary number 10 to a binary number 11 through the state machine when a second write command request is obtained during the flush operation.
In a second aspect, a device of marking dirty bits in an L2P table based on a solid state drive is provided, which including;
an obtaining module, configured for obtaining a marking request of dirty bits in the L2P table based on the solid state drive;
a broadening module, configured for broadening a corresponding dirty bit in the L2P table to 2 bits according to the request;
a first skipping module, configured for setting the dirty bit from a binary number 00 to a binary number 01 through a state machine when a first write command request is obtained, and setting the dirty bit from the binary number 01 to a binary number 10 through the state machine when flush operation starts; and
a second skipping module, configured for setting the dirty bit from the binary number 10 to a binary number 11 through the state machine when a second write command request is obtained during the flush operation.
In a third aspect, a computer device is provided, which including: a processor, and a computer program stored on the memory and operating on the processor, and the processor implements the steps of the method for marking dirty bits in an L2P table based on a solid state drive of the first aspect when the processor executes the computer program
In a fourth aspect, a computer readable storage medium is provided, the computer readable storage medium is stored thereon with a computer program, and the steps of the method for marking dirty bits in an L2P table based on a solid state drive of the first aspect are implemented when the computer program is executed by a processor.
The beneficial effects of the method and device for marking the dirty bits of the L2P table based on the SSD provided in the embodiments of the present application are: the present application by obtaining a marking request of dirty bits in the L2P table based on the solid state drive; and broadening a corresponding dirty bit in the L2P table to 2 bits according to the request; and setting the dirty bit from a binary number 00 to a binary number 01 through a state machine when a first write command request is obtained; setting the dirty bit from the binary number 01 to a binary number 10 through the state machine when flush operation starts; and setting the dirty bit from the binary number 10 to a binary number 11 through the state machine when a second write command request is obtained during the flush operation. The present application adopts a 2-bit dirty bit to represent 4 different states through the 2-bit dirty bit, and the skipping mechanism of the state machine is adopted to realize that there is no need to block write commands during flash programming, which is beneficial to improve write performance and reduce write latency.
In order to make the purpose, technical solutions, and advantages of the present application clearer, the following further describes the present application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and not used to limit the application.
In traditional technology, the dirty bit is 1 bit, and the L2P table in the cache is a copy of the L2P table in the flash. When the write command is executed, the system will update the L2P table in the cache, so that when the L2P table in the cache is inconsistent with the L2P table in the flash, in order to record the inconsistent information, setting the dirty bit. Later, when appropriate, the system flushes the L2P table in the cache to the flash. When the flush is completed, the L2P table in the cache and flash is consistent again, and the system clears the dirty bit to 0.
The whole process is shown in FIG. 1: At t0, a write command is executed, so the system modifies the L2P table in the cache, and the dirty bit is set to 1. At t1, the system initiates a flush operation and saves the L2P table at t1 to the flash, because it takes several hundred microseconds to program the flash, the flush is completed at t3. If the flash is successfully programmed at t3, it means that the L2P table in the flash is consistent with that in the cache, so the dirty bit is cleared. If the flash programming fails at t3, the dirty bit cannot be cleared and you need to choose an opportunity to initiate the flush again.
There is a loophole in this process: if at t2 between t1 and t3, a write command happens to modify the L2P table in the cache, the dirty bit will be 1, but if flush is successful at t3, the dirty bit will be cleared, at t3, it is actually succeeded in saving the L2P table in the cache at t1 to the flash, but at t2 the L2P table in the cache was changed again, so the L2P table in the cache and flash was inconsistent at t3, thereby, at t3, the dirty bit cannot be cleared. To solve this problem, the usual approach is to block the write command between t1 and t3, that is, not to execute the write command. This causes the write command that should be executed at t2 to be postponed to execute after t3, which affects performance and latency.
Based on above technical problem, the present application provides a method for marking dirty bits in an L2P table based on SSD, which realized that there is no need to block the write command during flash programming between t1 and t3, thereby write performance is improved, and latency is reduced.
In order to explain the content of the present application more clearly, the terms and abbreviations in this application are explained as follows:
SSD: Solid state drive;
flash: a non-volatile memory;
L2P table: Logic Page Address To Physical Page Address mapping table;
Dirty: characterizes whether the L2P table in the cache and flash is consistent, and if they are inconsistent, it is called dirty;
flush: In the present application, it specifically refers to programming the L2P table in the cache into the flash;
clear: In the present application, when the L2P table in the cache is successfully programmed into the flash, the dirty bit is marked as a non-dirty state.
bit: bit.
In an embodiment, as shown in
Step 202, obtaining a marking request of dirty bits in the L2P table based on the solid state drive;
Step 204, broadening a corresponding dirty bit in the L2P table to 2 bits according to the request;
Step 206, setting the dirty bit from a binary number 00 to a binary number 01 through a state machine when a first write command request is obtained;
Step 208, setting the dirty bit from the binary number 01 to a binary number 10 through the state machine when flush operation starts; and
Step 210, setting the dirty bit from the binary number 10 to a binary number 11 through the state machine when a second write command request is obtained during the flush operation.
Referring to the schematic diagram of the dirty bit state of the scenario where the write command occurs between t1 and t3 shown in
In an embodiment, as shown in
Step 212, setting the dirty bit from the binary number 11 to a binary number 01 through the state machine when the flush operation is finished.
Similarly, referring to the schematic diagram of the dirty bit state of the scenario where the write command occurs between t1 and t3 shown in
When the 1-bit dirty bit was originally used, after the L2P table flush starts and before the flush completes the dirty clearing, if the dirty bit is 1, the 1 state will be cleared by the following dirty clearing, so the dirty state will be lost. The traditional solution is to avoid the dirty bit being 1 after the start of the L2P table flush and before the flush completes the dirty clearing. In order to do this, it is necessary to prohibit processing write commands within the range of this L2P table for a while, so that the write commands are blocked, which affects write performance. After adopting the method of the present application, after the start of L2P table flush and before the flush completes the dirty clearing, the write commands within the range of this L2P table can still be processed without blocking and the dirty marking will not be lost, which is beneficial to improve the write performance and shorten the write command response time.
In the above embodiment, the dirty bit is widened from the traditional 1-bit to 2-bit, and a state machine is introduced, and the 2-bit dirty bit is treated as the state bit of the state machine, which can solve the problem of dirty being set to 1 after the L2P table flush is started and before dirty is cleared, thereby achieving the purpose of improving write performance and reducing write latency.
In an embodiment, as shown in
Step 402, obtaining a marking request of dirty bits in the L2P table based on the solid state drive;
Step 404, broadening a corresponding dirty bit in the L2P table to 2 bits according to the request;
Step 406, setting the dirty bit from a binary number 00 to a binary number 01 through a state machine when a first write command request is obtained;
Step 408, setting the dirty bit from the binary number 01 to a binary number 10 through the state machine when flush operation starts; and
Step 410, if the second write command request is not obtained during the flush operation, resetting the dirty bit from the binary number 10 to a binary number 00 through the state machine when flush operation is finished.
Referring to the schematic diagram of the dirty bit state of the scenario where no write command occurs between t1 and t3 shown in
In the above-mentioned embodiment, it can be seen from these two typical scenarios that the consistency problem of the dirty bits between write, flush and clear is solved, and the write command does not need to be blocked in the time period of t1 and t3, thereby improving the write performance and reducing write latency.
In an embodiment, as shown in
Step 502, marking a corresponding dirty bit state by a state of the state machine;
Step 504, if the dirty bit state is the binary number 00, it means that the L2P table in the cache and flash is consistent; and
Step 506, if the dirty bit state is the binary number 01 or 10 or 11, it means that the L2P table in the cache and flash is inconsistent.
In the present embodiment, by introducing a state machine, the 2-bits dirty bit is the state of the machine state, as shown in
There are four states of the state machine: binary numbers 00/01/10/11. It is understandable that the state machine can be realized not only by software, but also by hardware circuits, as long as it can realize a two-bit state skipping. Specifically, the state skipping mechanism of the state machine is shown in
It should be understood that although the various steps in the flowcharts of
In an embodiment, as shown in
an obtaining module 901, configured for obtaining a marking request of dirty bits in the L2P table based on the solid state drive;
a broadening module 902, configured for broadening a corresponding dirty bit in the L2P table to 2 bits according to the request;
a first skipping module 903, configured for setting the dirty bit from a binary number 00 to a binary number 01 through a state machine when a first write command request is obtained, and setting the dirty bit from the binary number 01 to a binary number 10 through the state machine when flush operation starts; and
a second skipping module 904, configured for setting the dirty bit from the binary number 10 to a binary number 11 through the state machine when a second write command request is obtained during the flush operation.
In an embodiment, the second skipping module 904 further configured for setting the dirty bit from the binary number 11 to a binary number 01 through the state machine when the flush operation is finished.
In an embodiment, the first skipping module 903 further configured for resetting the dirty bit from the binary number 10 to a binary number 00 through the state machine when flush operation is finished, if the second write command request is not obtained during the flush operation.
In an embodiment, as shown in
marking a corresponding dirty bit state by a state of the state machine;
if the dirty bit state is the binary number 00, it means that the L2P table in the cache and flash is consistent; and
if the dirty bit state is the binary number 01 or 10 or 11, it means that the L2P table in the cache and flash is inconsistent.
Regarding the specific definition of the device for marking dirty bits in an L2P table based on a solid state drive please refer to the above limitation on the method or marking dirty bits in an L2P table based on a solid state drive, which will not be repeated here.
In an embodiment, a computer device is provided, and its internal structure diagram may be as shown in
Those skilled in the art can understand that the structure shown in
In an embodiment, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory and capable of operating on the processor. The processor implements the steps in the above method embodiments when the computer program is executed.
In an embodiment, a computer readable storage medium is provided, on which a computer program is stored, and the computer program is executed by a processor to implement the steps in the above method embodiments.
A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage. In the medium, when the computer program is executed, it may include the procedures of the above-mentioned method embodiments. Among then, any reference to memory, storage, database, or other medium used in the embodiments provided in this application may include non-volatile and/or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not a limitation, RANI is available in many forms, such as static RAM (SRAM), dynamic RANI (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered as the range described in this specification.
The above-mentioned embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can be made, and these all fall within the protection scope of this application. Therefore, the scope of protection of the patent of this application shall be subject to the appended claims.
Number | Date | Country | Kind |
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201910876237.9 | Sep 2019 | CN | national |
The present application is a National Stage Application filed under USC 371 of International Patent Application No. PCT/CN2020/076772 with an international filing date of Feb. 26, 2020, designating the United States, now pending, and further claims the priority of CN patent application submitted at the Chinese Patent Office on Sep. 17, 2019, with application No. 201910876237.9, titled “method and device for marking dirty bits in L2P table based on solid state drive”, the whole contents each of which are incorporated herein by reference thereto.
Filing Document | Filing Date | Country | Kind |
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PCT/CN2020/076772 | 2/26/2020 | WO |