Preferred embodiments of the present invention will be described in detail by reference to the drawings, wherein:
A preferred embodiment of the present invention will now be described referring to the drawings.
Explanation of the Principle
There is another problem in that the noise of a drive signal used inside the panel is superposed on the pixel current. For example, as shown in
As described, the noise superposed on the PVdd current and CV current is in reversed phases regardless of whether the noise generating factor is inside or outside. Therefore, as shown in
When the noise current components appearing on the CV terminal and the PVdd terminal are set as a×N and b×N, respectively, where a and b are constants, currents iCV and iPVdd can be represented by:
iCV=iPix−a×N
iPVdd=iPix+b×N
Thus, in order to cancel the noise component, the following calculation can be performed:
The optimum values for the constants a and b depend on the resistance component of the line inside the panel, the floating capacitor, a configuration of the PVdd line and the cathode, noise component for which the noise reduction is most strongly desired, etc.
It is also possible to detect constants a and b by, for example, forcefully applying noise. When the values for constants a and b are determined, it is preferable to apply a weighted addition to determine (a+b)×iPix.
A signal generator circuit 10 generates image data and a control signal for causing the pixels to emit light, pixel by pixel, and measuring current, according to an instruction by a CPU 12. A CV terminal of a panel 14 is connected to a negative input terminal of an operational amplifier (OP amplifier) OP1 via a resistor R1. Because a CV voltage is input on a positive input terminal of the operational amplifier OP1 and an output is negatively fed back via a resistor R3, a voltage of (CV voltage−iCV×R3) is output on the output terminal of the operational amplifier OP1. A PVdd terminal of the panel 14 is connected to a negative input terminal of an operational amplifier OP2 via a resistor R2. Because the PVdd voltage is input on a positive input terminal of the operational amplifier OP2 and an output is negatively fed back via a resistor R4, a voltage of (PVdd voltage+iPVdd×R4) is output on an output terminal of the operational amplifier OP2.
The resistors R1 and R2 may be omitted, but by inserting these resisters R1 and R2, the gain of the circuit for the noise which is a voltage supply can be reduced while not affecting the direct current gain for the pixel current iPix. However, care must be taken as larger resistances of the resisters result in slower responses of output corresponding to iPix due to influences of capacitors within the panel (such as C1 and C2 in
The output terminals of the operational amplifiers OP1 and OP2 are connected to negative and positive input terminals of an operational amplifier OP3 via resistors R5 and R6, respectively. Therefore, the outputs of the operational amplifiers OP1 and OP2 are differentially amplified by the operational amplifier OP3, and a voltage represented by the following formula (Vadin) is obtained and is input to an A/D converter 16.
Vadin={(PVdd voltage+iPVdd·R4)·R8−Vr·R6}·(R5+R7)/R5·(R6+R8)−R7·(CV voltage−iCV·R3)/R5
The operational amplifier OP3 is negatively fed back via a resistor R7, and a reference voltage Vr is supplied to the positive input terminal of the operational amplifier OP3 via a resistor R8. The reference voltage Vr is set so as to achieve an optimum offset value to be input to an A/D converter at the downstream.
When R5 is set equal to R6 (R5=R6) and R7 is set equal to R8 (R7=R8), a voltage proportional to a difference between outputs of the operational amplifiers OP1 and OP2 is output at the output of the operational amplifier OP3, and thus Vadin becomes a voltage in which a DC offset of {(PVdd−CV)·R7/R5−Vr} is added to a weighted sum of iCV and iPVdd in a ratio of (R3:R4).
In other words, by setting the reference voltage Vr at an appropriate value, it is possible to set the DC offset value of the voltage input to the A/D converter 16 to a suitable voltage (for example, 0V), and a code corresponding to a voltage of (R3×iCV+R4×iPVdd)R7/R5 is obtained from the A/D converter 16. By setting the values of resistances R3 and R4 according to a ratio of the two instances of noise, the noise can be removed and a code corresponding to a voltage which is (R3+R4)R7/R5 times that of the drive current can be obtained.
The pixels are caused to emit light one by one, an amount of current for each pixel is detected, and a detected value or a compensation value based on the detected value is stored in a memory 18. During the actual display, the data signal to be supplied to each pixel is corrected based on the value stored in the memory 18 so that the variation among the pixels is compensated and suitable display is realized.
Number | Date | Country | Kind |
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2006-280280 | Oct 2006 | JP | national |