METHOD AND DEVICE FOR SIMPLIFIED SUCCESSIVE CANCELLATION LIST DECODING OF POLARIZATION-ADJUSTED CONVOLUTIONAL (PAC) CODES

Abstract

Methods and devices are provided in which a channel encoded with a polarization-adjusted convolutional (PAC) code is received. A decoded codeword is generated based at least in part on simplified successive cancellation list (SSCL) decoding performed on the channel via a decoding tree. The decoding tree includes a node that generates candidate codeword output based on predefined processing using convolutional code (CC) state input and channel vector input. A sub-tree of the node remains unprocessed.

Description

TECHNICAL FIELD

The disclosure generally relates to wireless communication systems. More particularly, the subject matter disclosed herein relates to improvements to channel coding schemes in wireless communication systems.

SUMMARY

5^th Generation (5G) communication systems have adopted polar codes as a channel coding scheme for control channels due to their modest encoding and decoding complexity.

Polarization-adjusted convolutional (PAC) codes have recently been proposed as a new polar coding scheme. Compared to polar codes, PAC codes encode data with a rate-1 convolutional code (CC) prior to applying a polar transform. Input to the CC encoder includes an information-carrier vector, a state of the encoder, and a generator polynomial. Output from the CC encoder may include a CC codeword and an updated state vector.

Successive cancellation (SC) is one of the most common polar code decoding algorithms. SC decoding operates on a decoding tree in which each node corresponds to a constituent code with a certain information set. SC list (SCL) decoding includes a number of parallel SC decoders that interact with each other at information bits. Unlike SC decoding, two possibilities are considered in SCL decoding. Additionally, in SCL decoding, the list size or number of parallel SC decoders may be expanded and pruned. PAC SCL decoding is similar to polar SCL decoding, with the difference being that, in PAC SCL decoding, two lists are maintained, and for each list member, a CC state and encoder state are stored.

In simplified SC/SCL (SSC/SSCL) decoding of a polar code, at special nodes of a decoding tree, a decoding result may be obtained without processing the sub-tree of the special node. This reduces decoding latency depending on the node type. The special nodes include a rate-0 note, a repetition node, a rate-1 node, and a single parity check (SPC) node. The rate-0 node is defined as a node having leaf nodes that are all frozen or zero-valued bits. A repetition node is defined as a node having frozen leaf nodes except for a last leaf node that includes information or a one-valued bit. A rate-1 node is defined as a node having leaf nodes that all include information or one-valued bits. An SPC node is defined as a node having leaf nodes with information except for a first leaf node that is frozen or a zero-valued bit.

One issue with the above approach is that it is not possible to apply the special node decoding to PAC codes due to the CC encoding. For example, if the special node decoding were applied to PAC codes, the output of a rate-0 node would not be all zero, the output of a repetition node would not be all zero or all 1, the rate-1 node would be a non-linear code requiring special handling, and the output of an SPS node would not be from an SPC codebook.

To overcome these issues, systems and methods are described herein for development of an SSCL decoder for PAC codes considering the four special node types.

Specifically, methods are provided to process the special nodes at the node level considering the impact of CC encoding. The output of a rate-0 node is a constant codeword for each list member. The output of a repetition node is one of two constant codewords for each list member. The output of a rate-1 node may be decoded with techniques available for polar code. A least likelihood ratio (LLR) scrambling method is provided for decoding an SPC node. Methods are also provided to implement inverse CC encoding with lower complexity across the special node lengths.

In an embodiment, a method is provided in which an electronic device receives a channel encoded with a PAC code. A decoded codeword is generated based at least in part on SSCL decoding performed, by the electronic device, on the channel via a decoding tree. The decoding tree includes a node that generates candidate codeword output based on predefined processing using CC state input and channel vector input. A sub-tree of the node remains unprocessed.

In an embodiment, an electronic device is provided that includes a receiver configured to receive a channel encoded with a PAC code. The electronic device also includes a decoder configured to generate a decoded codeword based at least in part on SSCL decoding performed on the channel via a decoding tree. The decoding tree includes a node that generates candidate codeword output based on predefined processing using CC state input and channel vector input. A sub-tree of the node remains unprocessed.

In an embodiment, an electronic device is provided that includes a processor and a non-transitory computer readable storage medium storing instructions that, when executed, cause the processor to receive a channel encoded with a PAC code, and generate a decoded codeword based at least in part on SSCL decoding performed on the channel via a decoding tree. The decoding tree includes a node that generates candidate codeword output based on predefined processing using convolutional code (CC) state input and channel vector input. A sub-tree of the node remains unprocessed.

BRIEF DESCRIPTION OF THE DRAWING

In the following section, the aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments illustrated in the figures, in which:

FIG. 1 is a diagram illustrating a communication system, according to an embodiment;

FIG. 2 is a diagram illustrating a PAC encoder, according to an embodiment;

FIG. 3 is a diagram illustrating a decoding tree for a polar code, according to an embodiment;

FIG. 4 is a diagram illustrating a decoding tree for a PAC code, according to an embodiment;

FIG. 5 is a flowchart illustrating a method of SSCL decoding of a PAC code, according to an embodiment; and

FIG. 6 is a block diagram of an electronic device in a network environment, according to an embodiment.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail to not obscure the subject matter disclosed herein.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) in various places throughout this specification may not necessarily all be referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. Similarly, a hyphenated term (e.g., “two-dimensional,” “pre-determined,” “pixel-specific,” etc.) may be occasionally interchangeably used with a corresponding non-hyphenated version (e.g., “two dimensional,” “predetermined,” “pixel specific,” etc.), and a capitalized entry (e.g., “Counter Clock,” “Row Select,” “PIXOUT,” etc.) may be interchangeably used with a corresponding non-capitalized version (e.g., “counter clock,” “row select,” “pixout,” etc.). Such occasional interchangeable uses shall not be considered inconsistent with each other.

Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity.

Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.

The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element or layer is referred to as being on, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/of” includes any and all combinations of one or more of the associated listed items.

The terms “first,” “second,” etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and ease of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term “module” refers to any combination of software, firmware and/or hardware configured to provide the functionality described herein in connection with a module. For example, software may be embodied as a software package, code and/or instruction set or instructions, and the term “hardware,” as used in any implementation described herein, may include, for example, singly or in any combination, an assembly, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, but not limited to, an integrated circuit (IC), system on-a-chip (SoC), an assembly, and so forth.

FIG. 1 is a diagram illustrating a communication system, according to an embodiment. In the architecture illustrated in FIG. 1, a transmitting device 102 includes a first processor 106 in communication with an encoder 108. The transmitting device 102 is in communication with a receiving device 104, which includes a second processor 110 and a decoder 112. The encoder 108 may encode messages (or message-words) into codewords that are sent from the transmitting device 102 to the receiving device 104. The decoder 112 may decode received codewords into messages (or message-words) at the receiving device 104.

FIG. 2 is a diagram illustrating a PAC encoder, according to an embodiment. A message word d₁^K may be rate profiled at first block 202 to a length-N=2ⁿ word v₁^N. Rate profiling refers to the determination of K indices in vector v and the placement of K message bits in those indices of vector v. Specifically, vector v has K message bits and N−K frozen bits with zero values. The information bit indices are provided by an information set of cardinality K. The frozen set is denoted as ={1, . . . , N}\. A rate-1 convolutional encoder with generator polynomial =(₀, . . . , _m) may be applied on vector v at second block 204, which outputs a length-N vector u₁^N. With respect to the generator polynomial, ₀=_m=1. The parameter m is the number of memory units of the convolutional code and m+1 is the constraint length. This results in Equation (1) below.

$\begin{array}{cc}{u}_i={\sum }_{j=0}^{i-1}{g}_j{v}_{i-j}.& \left(1\right)\end{array}$

Equivalently, u₁^N=v₁^N·G_cc, result ation (2) below.

$\begin{array}{cc}{G}_{\mathrm{cc}}=\left[\begin{array}{cccccc}{g}_0& \cdots & g_m& 0& \cdots & 0\\ 0& g_0& \cdots & g_m& 0& 0\\ 0& 0& g_0& \cdots & g_m& 0\\ 0& 0& 0& g_0& \cdots & g_m\\ 0& 0& 0& 0& g_0& \cdots \\ 0& 0& 0& 0& 0& g_0\end{array}\right]& \left(2\right)\end{array}$

Another equivalent description may be provided through a state vector and an input bit at a given time. The state vector is a length-m vector that contains the input bits to the convolutional encoder. At time i, when the input to the encoder is v₁, the state vector is State_i=(v_i−1, . . . , v_i−m). The output bit u_i may be determined from the input bit v_i, the current state vector, and the generator polynomial of the code . This function may be referred to as ConvTrans(·) and also returns the next state, as shown in Equation (3) below.

$\begin{array}{cc}\left(u_i,\mathrm{next\_State}\right)=\mathrm{ConvTrans}\left(v_i,\mathrm{current\_State},g\right)& \left(3\right)\end{array}$

A generator matrix of length-N(N=2ⁿ) polar code may be

$G_N=F^{\otimes n}\mathrm{where}F=\left[\begin{array}{cc}1& 0\\ 1& 1\end{array}\right].$

Vector u may then be encoded using a polar code of length N to obtain a final codeword c=(c₁, . . . , c_N)=uG_N. A received word at the output of the channel may be denoted as y=(y₁, . . . , y_N).

SC decoding of PAC codes is similar to SC decoding of polar codes. With respect to SC decoding of polar codes, a polar code of length N and message word length K may be associated with an information set _N of cardinality K containing indices of information bits, which in turn determines the N−K indices of frozen bits, which are always set to zero. An SC polar decoder takes a channel LLR vector (λ₁, . . . , λ_N) and the information set as input, and outputs a decoded message word û that contains the K decoded message bits at the indices given by the information set and N−K zero-valued bits at the indices given by the frozen set. The SC decoder may be defined recursively as follows.

To obtain û=SC_dec(λ₁, . . . , λ_N, _N, a length-N/2 upper polar code may be decoded with inputs to the SC decoder, as shown in Equations (4) and (5) below.

$\begin{array}{cc}\left({\lambda }_1^{\left(\mathrm{up}\right)},\dots ,{\lambda }_{\frac{N}{2}}^{\left(\mathrm{up}\right)}\right),\mathrm{and}{\frac{N}{2}}_{\left(\mathrm{up}\right)}^{}& \left(4\right)\end{array}$ $\mathrm{where}$ $\begin{array}{cc}{\lambda }_i^{\left(\mathrm{up}\right)}={\lambda }_i{\lambda }_{i+N/2}& \left(5\right)\end{array}$

The operator is a box-plus operator, also referred to as a check-node operator, which is defined as

$xy=2{\tanh }^{-1}\left(\tanh \frac{x}{2}.\tanh \frac{y}{2}\right).$

The check-node operator may also be defined as an approximation of Equation (6) below.

$\begin{array}{cc}xy=\mathrm{Sign}\left(x\right)\mathrm{Sign}\left(y\right)·\min \left(❘x❘,❘y❘\right)& \left(6\right)\end{array}$

where Sign(α) is equal to 1 for α>0 and −1 for α<0.

The set

${\frac{N}{2}}_{\left(\mathrm{up}\right)}^{}$

may be defined as

${\frac{N}{2}}_{\left(up\right)}^{}=\left\{i|i\in N_{},i\le \frac{N}{2}\right\}.$

Once the upper code is decoded and the decoded message word û^(up) is obtained, it may be encoded by G_N/2 to obtain the corresponding codeword as ĉ^(up)=û^(up)G_N/2=(ĉ₁^(up)), . . . , ĉ_N/2^(up)). A lower length-N/2 polar code may then be decoded with inputs to the SC decoder, as shown in Equations (7) and (8) below.

$\begin{array}{cc}\left({\lambda }_1^{\left(lo\right)},\dots ,{\lambda }_{\frac{N}{2}}^{\left(\mathrm{lo}\right)}\right)\mathrm{and}{\frac{N}{2}}_{\left(\mathrm{lo}\right)}^{}& \left(7\right)\end{array}$ $\mathrm{where}$ $\begin{array}{cc}{\lambda }_1^{\left(lo\right)}=\left(1-2{\hat{c}}_1^{\left(up\right)}\right){\lambda }_i+{\lambda }_{i+N/2}& \left(8\right)\end{array}$

The set

${\frac{N}{2}}_{\left(lo\right)}^{}$

may be defined as

${\frac{N}{2}}_{\left(lo\right)}^{}=\left\{i-\frac{N}{2}\in |i\in A_N,i>\frac{N}{2}\right\}.$

This decoder may provide the decoded message word as û^(lo). The final decoding output for the length-N polar code may then be obtained as shown in Equation (9) below.

$\begin{array}{cc}\hat{u}=\left({\hat{u}}^{\left(up\right)},{\hat{u}}^{\left(up\right)}\right)& \left(9\right)\end{array}$

The above-described recursive decoder may stop at length N=1 for which the rule of Equation (10) may be used for decoding.

$\begin{array}{cc}{\hat{u}}_1=\{\begin{array}{cc}0& i\notin 1_{}\\ \frac{1-\mathrm{Sign}\left({\lambda }_1\right)}{2}& i\in 1_{}\end{array}& \left(10\right)\end{array}$

FIG. 3 is a diagram illustrating a decoding tree for a polar code, according to an embodiment. The above-described SC decoding may also be viewed as operating on the decoding tree. The decoding tree of FIG. 3 may be a length-8 decoding tree, or a portion of larger decoding tree. For a length-8 decoding tree, a length-8 polar code may correspond to a first node 302. Second and third nodes 304 and 306, to the immediate left of the first node 302, may each correspond to a length-4 polar code. Fourth, fifth, sixth, and seventh nodes 308, 310, 312, and 314 may each correspond to a length-2 polar code. Eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth nodes 316, 318, 320, 322, 324, 326, 328, and 330, at the leftmost side of the decoding tree, may each correspond to a length-1 polar code, and may be referred to as leaf nodes. SC decoding may be viewed as processing every node in the decoding tree in a specific order, starting from the rightmost length-N node 302. A length N=2ⁿ polar code has a decoding tree with n+1 columns where there are 1 length-N node at the rightmost column, 2 length-N/2 nodes at the second rightmost column, and so on. The leftmost column has N nodes corresponding to length-1 polar codes. Channel LLR λ⁽ⁱ⁾ is provided downstream through the nodes and candidate decoded codewords β⁽ⁱ⁾ are provided upstream through the nodes.

SC decoding of PAC codes is essentially the same as SC decoding of polar codes with an additional step to consider for the CC encoder. Additionally, a CC encoder is run at the SC decoder. The CC encoder may be realized by a sequential calling of Equation (3).

The SC decoder may initialize the states of the CC encoder as all-zero. The decoding proceeds as it does for polar codes. Once the LLR λ⁽ⁱ⁾ is calculated at the bit index, i, v_i and u_i may be determined according to one of the cases below.

In a first case, i∉_N:(u_i,next_State)=ConvTrans(v_i=0,current_State,). Then current_State may be set as next_State.

In a second case, i∈_N, two possibilities may be considered for v_i=0, and v_i and u_i is calculated for each as shown in Equations (11) and (12) below.

$\begin{array}{cc}\left(u_i^{\left(0\right)},\mathrm{next\_State}\_0\right))=\mathrm{ConvTrans}\left(v_i=0,\mathrm{current\_State},g\right)& \left(11\right)\end{array}$ $\begin{array}{cc}\left(u_i^{\left(1\right)},\mathrm{next\_State}\_1\right))=\mathrm{ConvTrans}\left(v_i=1,\mathrm{current\_State},g\right)& \left(12\right)\end{array}$

v_i may then be determined as shown in Equation (13) below.

$\begin{array}{cc}{v}_i=\{\begin{array}{cc}0& \left(1-2u_i^{\left(0\right)}\right){\lambda }_i\ge 0\\ 1& \left(1-2u_i^{\left(0\right)}\right){\lambda }_i<0\end{array}& \left(13\right)\end{array}$

and u_i=u_i^(vi). The CC state may also be updated as next_State_0 if v_i=0, and otherwise, as next_State_1.

SSC decoding of polar codes takes advantage of the special nature of the code corresponding to a node in the decoding tree, so as to avoid the necessity of traversing all the way down to the leaf nodes and calculate the LLRs at the information bits. In case of a special node, SC decoding may be temporarily taken over by the decoder of the special node until the special decoding results are passed to the SC decoder, at which point SC decoder may resume.

For example, a polar code of length 16 may include four polar codes of length 4, each with their corresponding rates. A complete decoding tree for this code has five columns of nodes, with 16 nodes at the left most column.

Typically, at node i, the SC decoder may proceed to the leaf nodes (each node #i has two more levels of branching resulting in eight leaf nodes in FIG. 3). However, if the code corresponding to the node is considered special, then traversing to the leaf nodes may be avoided.

For example, referring to FIG. 3, the fourth node 308 may be considered a rate-0 (or all-zero) special node because the information/frozen pattern for the corresponding leaf nodes 318 and 320 are each frozen or a zero-valued bit. The second node 304 may be considered a repetition special node because the information/frozen pattern for the corresponding leaf nodes 318, 320, 322, and 324 are frozen or zero-valued bits for all but the last leaf node 326, which has information or a one-valued bit. The seventh node 314 may be considered a rate-1 special node because the information/frozen pattern for the corresponding leaf nodes 328 and 330 are each information or a one-valued bit. The third node 306 may be considered an SPC special node because the information/frozen pattern for the corresponding leaf nodes 324, 326, 328, and 330 is information or one-valued bit for all but the first leaf node 324, which is frozen or a zero-valued bit.

As the code at the second node 304 is a repetition code of length-4, two possible codewords may be decoded at the node level, by only calculating a machine-learning (ML) metric for codeword (0,0,0,0) and (1,1,1,1). The path metrics may also be calculated at the node level. The output of the special decoder may be passed to the SC decoder, which proceeds to the third code corresponding to the third node 306.

The SCL decoding of polar codes is based on the idea that at each information bit index, a final decision is not made, but rather a list of possibilities based on the two values of the bits are considered. In particular, SCL decoding with a list size of L, stores a list of size L after decoding the bit index i. The list has L path members, each having a length i, containing decoded values of bits u₁, . . . , u_i. At frozen bits, the list may be expanded by padding zero to the current list, making it one unit longer. Path metrics may be updated for each member of the new list. At information bits, the current list may be expanded to give a list of 2L paths by appending 0 and 1 to each path in the list. A path metric is calculated for each of the 2L new paths. The L paths with the smallest metrics may be kept in the list, while the L paths with the largest metrics may be removed from the expanded list, resulting in a new list of size L, containing members which are 1 bit longer than the previous list. This process may continue until the length of the paths in the list reaches N. At this step, the path with the smallest metric is chosen as the final candidate (i.e., decoder output).

SCL decoding of polar codes may be improved by appending cyclic redundancy check (CRC) to the message word u. The resulting decoding scheme may be referred to as CRC-aided SCL (CA-SCL) decoding. Compared to SCL decoding, CA-SCL decoding may select the final decoded word from the final list given at the bit index N, as the path with smallest path metric that satisfies the CRC.

SCL decoding of PAC codes is essentially the same as SCL decoding of polar codes with the modification that L running CC encoders are kept at the decoder. Two lists are stored for v and u. The list expansion at the frozen bits for SCL decoding of PAC codes is performed in a manner similar to that for SC decoding of PAC codes. Similarly, at the information bits, the list may be expanded by considering two possibilities 0 and 1 for the v list and obtaining the corresponding expanded u list. The path metrics may be calculated based on the calculated LLRs and the u list. The remainder of the procedure is similar to SCL decoding of polar codes. CA-SCL decoding of PAC codes is with the modification of the SCL decoding, where the modification is based on the appended CRC as described in the CA-SCL decoding of polar codes.

According to an embodiment, an SSCL decoding algorithm is proposed for the PAC codes, which defines how to process a special node for the PAC code in SCL decoding. After processing bit number i, an SCL decoder may have L (list size) path members of v (referred to as v-list), L path members of u (referred to as u-list), corresponding path metrics (PMs), intermediate LLRs, and encoded message bits for each path member in the decoding graph. The decoder may process a special node of length M=2^m with a starting index i for a first bit the decoding tree. For each path member that is of size i−1 bits, simplified processing of the next node may be performed. For each path member prior to processing of the special node, the decoder may have information including a estate vector Curr_State, the LLR vector at the output of the node, λ₀, . . . , λ_M−1, and path metric value PM.

FIG. 4 is a diagram illustrating a decoding tree for a PAC code, according to an embodiment. Unlike the decoding tree for polar code shown in FIG. 3, an input CC state (cState_in) and an output CC state (cState_out) are provided to and from the nodes of the decoding tree for PAC code. The decoding tree of FIG. 4 may be a length-4 decoding tree or a portion of a larger decoding tree. For a length-4 decoding tree, a length-4 PAC code may correspond to a first node 402. Second and third nodes 404 and 406, to the immediate left of the first node 402, may each correspond to a length-2 PAC code. Fourth, fifth, sixth, and seventh nodes 408, 410, 412, and 414, at the leftmost side of the decoding tree, may each correspond to a length-1 PAC code, and may be referred to as leaf nodes. An individual node (e.g., the second node 404) may receive a channel LLR λ⁽ⁱ⁾ vector and a current CC state cState_in from the first node 402. The node may output (e.g., to the first node 402) a candidate codeword β⁽ⁱ⁾ and a next CC state cState_out (as well as vector u and vector v).

The input to the CC encoder may be v=[v₀, . . . , v_M−1] and the output of the CC may be u=[u₀, . . . , u_M−1]. The codeword at the output of the special node may be denoted by c=[c₀, . . . , c_M−1]F^⊗m.

A node may be considered an all-zero special node if the information/frozen pattern at that node is an-all-zero vector of length M. The input to the CC may be a length-M word v=0.

The list may be expanded by appending a polar codeword corresponding to the output of the CC to the list member. The output of CC, v, is calculated as set forth in Equation (14) below.

Current_state_l= Curr_State //the state prior to processing the node.
For j = 0: M − 1
(ui, Current_state_l ) ← ConvTrans(vi, Current_state_l, g)
Return u
...(14)

Subsequently, u may be encoded to obtain c=u. G_M. The expanded path may be determined by concatenating v, u to the v-list and u-list, respectively.

The new path metric PM₀ may be calculated as shown in Equation (15) below.

$\begin{array}{cc}{\mathrm{PM}}_0\leftarrow \mathrm{PM}+\sum _{i=0}^{M-1}\frac{1-\mathrm{Sign}\left(\left(1-2c_i\right){\lambda }_i\right)}{2}❘{\lambda }_i❘& \left(15\right)\end{array}$

A node may be considered a repetition special node if the information/frozen pattern at that node is all zero in the first M−1 indices and 1 at the last index. The input to the CC may be a length-M word v, resulting in v=[0_1×M−1, v_M−1].

For two possibilities of v_M−1=0,1, v-list may be expanded by concatenating v⁽⁰⁾=[v₀⁽⁰⁾), . . . , v_M−1⁽⁰⁾]=[0_1×M−1, 0] and v⁽¹⁾=[v₀⁽¹⁾, . . . , v_M−1⁽¹⁾]=[0_1×M−1, 1] to a current v-list, resulting in two child paths. To obtain the u-list, the output of CC for the two possibilities may be calculated as set forth in Equation (16) below.

For l = 0: 1
Current_state_l= Curr_State //the state prior to processing the node:
This is same for both l = 0 and l
For j = 0: M − 1
(ui(l), Curr_State_l ) ← ConvTrans(vi(l), Curr_State_l, g)
u(l) = [u0(l), ... , uM−1(l)]
Return u(0) and u(1)
...(16)

As an alternative, u⁽⁰⁾ may be calculated according to the procedure above. u⁽¹⁾ is identical to u⁽⁰⁾ except for the last element where u_M−1⁽¹⁾=u_M−1⁽⁰⁾+1 (GF field or mode 2 operation) because g=1.

The u-list may be expanded by concatenating u⁽⁰⁾ and u⁽¹⁾ to a current u-list.

The path metrics of the two child paths, denoted by PM₀ and PM₁ may be calculated as shown in Equation (17) below.

$\begin{array}{cc}{\mathrm{PM}}_l\leftarrow \mathrm{PM}+\sum _{i=0}^{M-1}\frac{1-\mathrm{Sign}\left(\left(1-2c_i^{\left(l\right)}\right){\lambda }_i\right)}{2}❘{\lambda }_i❘& \left(17\right)\end{array}$

where c^(l)=[c₀^(l)], . . . , c_M−1^(l)=u^(l)G_M is the codeword at the output of special node (i.e., after applying polar transform).

It may also be possible to only perform polar encoding once and obtain c⁽⁰⁾, and calculate c⁽¹⁾ from c⁽⁰⁾ as follows. Since u⁽⁰⁾ and u⁽¹⁾ except for the last element for which u_M−1⁽¹⁾=u_M−1⁽⁰⁾+1, it may be shown that c⁽¹⁾=c⁽⁰⁾+1, where 1 is a length-M all-1 vector.

A node may be considered a rate-1 special node if the information/frozen pattern at that node is all-one. The input to the CC may be a length-M word v, resulting in v=[v₀, . . . , v_M−1], where all v_i are message bits from the message word d₁^K.

The codeword at the output of the special node, after polar transformation, c, may take any arbitrary vector in {0,1}^M. That is, a rate-1 code is provided even in the presence of the CC code. u_i is a linear combination of v_j,j≤i and the coefficient of the v_i is equal to 1, due to g=1. Therefore, u may be written as Equation (18) below.

$\begin{array}{cc}u=v{G}_{cc}+\eta & \left(18\right)\end{array}$

where η=[η₀, . . . , η_M−1] is a constant vector, whose elements are determined as a linear combination of the elements of the current path member, and G_cc is the generator matrix of the CC code, which is invertible and upper triangular. Therefore, u may be an arbitrary vector in {0,1}^M. Since c=uG_M, the same statement holds for c. The child path members may then be produced by having most likely estimated word c⁽⁰⁾, c⁽¹⁾, . . . , c^(Z−1) for Z child paths expansion.

The generation of child paths at the output of the special node after applying the polar transform may be performed according to the classical polar codes, as shown in Equation (19) below.

$\begin{array}{cc}\left[c^{\left(0\right)},c^{\left(1\right)},\dots ,c^{\left(Z-1\right)}\right]=\mathrm{Classical\_polar}\mathrm{\_Rate1}\mathrm{\_dec}\left({\lambda }_0,\dots ,{\lambda }_{M-1}\right)& \left(19\right)\end{array}$

The routine Classical_polar_Rate1 may take the M channel LLRs and output the most likely codewords of a rate-1 code. For example, the most likely codeword may be the result of hard decision on the LLRs. The second most likely codeword may be obtained by flipping a sign of smallest absolute value LLR and then taking hard decision. The third most likely codeword may be obtained by flipping the sign of the second smallest absolute value LLR. The fourth most likely codeword may be obtained by flipping the sign of the third smallest absolute value LLR, or flipping the signs of both the smallest and second smallest absolute value LLR.

The path metric PM_l corresponding toe each of the c^(l) may be calculated as shown in Equation (20) below.

$\begin{array}{cc}{\mathrm{PM}}_l\leftarrow \mathrm{PM}+{\sum }_{i=0}^{M-1}\frac{1-\mathrm{Sign}\left(\left(1-2c_i^{\left(l\right)}\right){\lambda }_i\right)}{2}❘{\lambda }_i❘\mathrm{for}l=0,\dots ,Z-1& \left(20\right)\end{array}$

For the expansion of the u-list and v-list, the corresponding u^(l) and v^(l) vectors that are mapped to c^(l) may be calculated in three steps.

In a first step, u^(l) may be calculated. Since c^(l)=u^(l)G_M and G_m⁻¹=G_m, as a property of polar generator matrix, Equation (21) may be conducted by a length-M polar encoding.

$\begin{array}{cc}{u}^{\left(l\right)}=c^{\left(l\right)}{G}_M& \left(21\right)\end{array}$

In a second step, the scrambling word η may be calculated. The word η may be referred to as a scrambling word as it scrambles the output of the CC encoder that would have been obtained if the encoder started at an all-zero state. To calculate η, CC may be a linear operator. Therefore, η may be equal to the output of the CC encoder for a length-M all-zero input word and initial encoder state given by Curr_State, as shown in Equation (22) below.

$\begin{array}{cc}\mathrm{Current\_state}\mathrm{\_l}=\mathrm{Curr\_State}.& \left(22\right)\end{array}$ $\mathrm{For}j=0:M-1$ $\left({\eta }_i,\mathrm{Curr\_State}\mathrm{\_l}\right)\leftarrow \mathrm{ConvTrans}\left(0,\mathrm{Curr\_State}\mathrm{\_l},g\right)$ $\mathrm{Return}\eta =\left[{\eta }_0,\dots ,{\eta }_{M-1}\right]$

In a third step, v^(l) may be calculated. Equations (23) and (24) are provided below.

$\begin{array}{cc}{u}^{\left(l\right)}=v^{\left(l\right)}{G}_{cc}+\eta ,\mathrm{or}& \left(23\right)\end{array}$ $\begin{array}{cc}{\tilde{u}}^{\left(l\right)}=v^{\left(l\right)}{G}_{cc}& \left(24\right)\end{array}$

where ũ^(l)=u^(l)+η, solving the Equation for v^(l) given ũ^(l).

According to a first solution using an inverse of G_cc, since G_cc is of size M×M and full-rank, it may be invertible. The inverse matrix may be calculated offline and stored for each special node length M. The v^(l) may then be calculated as v^(l)=ũ^(l)G_cc⁻¹.

According to a second solution using a shift register, numerical results may demonstrate that G_cc⁻¹ has the same structure as G_cc. In particular, both are Toeplitz matrices. That is, it may be described via a convolutional code generator polynomial. An example is shown in Equations (25) and (26) below for =(1,0,0,1) and M=8.

$\begin{array}{cc}{G}_{cc}=\left[\begin{array}{cccccccc}0& 1& 0& 0& 1& 0& 0& 0\\ 0& 0& 1& 0& 0& 1& 0& 0\\ 0& 0& 0& 1& 0& 0& 1& 0\\ 0& 0& 0& 0& 1& 0& 0& 1\\ 0& 0& 0& 0& 0& 1& 0& 0\\ 0& 0& 0& 0& 0& 0& 1& 0\end{array}\right]& \left(25\right)\end{array}$ $\begin{array}{cc}{G}_{cc}^{-1}=\left[\begin{array}{cccccccc}0& 1& 0& 0& 1& 0& 0& 1\\ 0& 0& 1& 0& 0& 1& 0& 0\\ 0& 0& 0& 1& 0& 0& 1& 0\\ 0& 0& 0& 0& 1& 0& 0& 1\\ 0& 0& 0& 0& 0& 1& 0& 0\\ 0& 0& 0& 0& 0& 0& 1& 0\end{array}\right]& \left(26\right)\end{array}$

This corresponds to a CC with generator polynomial g⁻¹=(1,0,0,1,0,0,1). If this is always the case, as described in greater detail below, the inverse generator polynomial may be found offline and then used to encode ũ^(l) and obtain v^(l).

Once v^(l) and u^(l) are calculated for l=0, . . . , Z−1, they may be appended to the current path member to obtain z child path members.

A node may be considered an SPC special node if the information/frozen pattern at that node is all-one except for the first index which is 0. The input to the CC may be a length-M word v, resulting in v=[v₀, . . . , v_M−1], where all the v_i are message bits from the message word d₁^K except for v₀=0.

Similar to the analysis for rate-1 node, Equation (27) is provided below.

$\begin{array}{cc}u=v{G}_{cc}+\eta & \left(27\right)\end{array}$

where η=[η₀, . . . , η_M−1] is a constant vector, whose elements are determined as a linear combination of the elements of the current path member, and G_cc is the generator matrix of the CC code which is invertible and upper triangular. η may be determined as described for rate-1 node.

Encoding u with the polar code corresponding to the special node, results in the codeword set forth in Equation (28) below.

$\begin{array}{cc}c=u{G}_M=\left(v{G}_{cc}+\eta \right)G_M=v{G}_{cc}{G}_M+\eta G_M& \left(28\right)\end{array}$ $c=v_{cc}{G}_M+{\eta }_c$

The vector v_cc=vG_cc has its first element as frozen (i.e., it always takes zero value). The first element is equal to v₀₀=0·₀=0.

Defining {tilde over (c)}=({tilde over (c)}₀, . . . , {tilde over (c)}_M−1) c+η_c results in {tilde over (c)}=v_ccG_M, which is a codeword of the SPC code. The child path members may then be calculated using methods for classical polar codes with an additional LLR scrambling with the binary sequence η_c. Steps for child path member generation are set forth below.

In a first step, a coded scrambling vector η_c may be calculated. η may be calculated as described above. η_c=(η_c,0, . . . , η_c,M−1) may be calculated via polar encoding as η_c=ηG_M.

In a second step the LLRs may be scrambled. The LLR vector (λ₀, . . . , λ_M−1) may be scrambled with η_c to obtain scrambled LLRs ({tilde over (λ)}₀, . . . , {tilde over (λ)}_M−1), which correspond to the scrambled codeword {tilde over (c)}. Scrambling may be performed as {tilde over (λ)}_i=(1−2η_c,i)λ_i. Methods for generation of child members of SPC code for classical polar code may be used to obtain Z child members as shown in Equation (29) below.

$\begin{array}{cc}\left[{\tilde{c}}^{\left(0\right)},{\tilde{c}}^{\left(1\right)},\dots ,{\tilde{c}}^{\left(Z-1\right)}\right]=\mathrm{Classical\_polar}\mathrm{\_SPC}\mathrm{\_dec}\left({\tilde{\lambda }}_0,\dots ,{\tilde{\lambda }}_{M-1}\right)& \left(29\right)\end{array}$

where {tilde over (c)}^(l)=({tilde over (c)}₀^(l), . . . , {tilde over (c)}_M−1^(l)) is the candidate for list member index l.

The corresponding path metrics PM_l are a function of PM and scrambled LLRs ({tilde over (λ)}₀, . . . , {tilde over (λ)}_M−1). The path metric PM_l corresponding to each of the {tilde over (c)}^(l) is calculated as shown in Equation (30) below.

$\begin{array}{cc}{\mathrm{PM}}_l\leftarrow \mathrm{PM}+{\sum }_{i=0}^{M-1}\frac{1-\mathrm{Sign}\left(\left(1-2{\tilde{c}}_i^{\left(l\right)}\right){\tilde{\lambda }}_i\right)}{2}❘{\lambda }_i❘\mathrm{for}l=0,\dots ,Z-1.& \left(30\right)\end{array}$

In a third step, v_cc may be calculated as v_cc^(l)={tilde over (c)}^(l)G_M for l=0, . . . , Z−1.

In a fourth step, v-list may be calculated. From v_cc=vG_cc, Equation (31) may be calculated as shown below.

$\begin{array}{cc}{v}^{\left(l\right)}=v_{cc}^{\left(l\right)}{G}_{cc}^{-1}\mathrm{for}l=0,\dots ,Z-1& \left(31\right)\end{array}$

As described above, the computation may be calculated with low complexity via shift registers without any matrix multiplication. The application of

${\mathrm{Classical}}_{{\mathrm{polar}}_{{\mathrm{SPC}}_{\mathrm{dec}(.)}}}$

ensures that the first element of v_cc^(l) and in turn the first element of v^(l) is zero for every l.

The expanded path v-list may be obtained by concatenating v^(l) to the current v-list for l=0, . . . Z−1.

In a fifth step, u-list may be calculated. To calculate the expanded path u-list, u^(l) may first be calculated as set forth in Equation (32) below.

$\begin{array}{cc}\mathrm{For}l=0:Z-1& \left(32\right)\end{array}$ $\mathrm{Current\_state}\mathrm{\_l}=\mathrm{Curr\_State}//\mathrm{the}\mathrm{state}\mathrm{prior}\mathrm{to}\mathrm{processing}\mathrm{the}\mathrm{node}:\mathrm{This}\mathrm{is}\mathrm{same}\mathrm{for}\mathrm{all}\mathrm{child}\mathrm{path}$ $\mathrm{index}l$ $\mathrm{For}j=0:M-1$ $\left(u_i^{\left(l\right)},\mathrm{Curr\_State}\mathrm{\_l}\right)\leftarrow \mathrm{ConvTrans}\left(v_i^{\left(l\right)},\mathrm{Curr\_State}\mathrm{\_l},g\right)$ $u^{\left(l\right)}=\left[u_0^{\left(l\right)},\dots ,u_{M-1}^{\left(l\right)}\right]$ $\mathrm{Return}{u}^{\left(0\right)},\dots ,u^{\left(Z-1\right)}$

Alternatively, u^(l) may be calculated as u^(l)=v_cc^(l)+η for l=0, . . . , Z−1.

The expanded path u-list may be obtained by concatenating u^(l) to the current u-list for l=0, . . . Z−1.

With respect to inverse operation of the CC encoder, the task of finding the input vector to the rate-1 CC encoder from the encoded output vector may be performed via another CC encoder (i.e., shift register and linear time). In particular, the inverse of Equation (33) takes the form of Equation (34), as shown below.

$\begin{array}{cc}{G}_N=\left[\begin{array}{cccccc}{g}_0& \dots & g_m& 0& \dots & 0\\ 0& g_0& \dots & g_m& 0& 0\\ 0& 0& g_0& \dots & g_m& 0\\ 0& 0& 0& g_0& \dots & g_m\\ 0& 0& 0& 0& g_0& \dots \\ 0& 0& 0& 0& 0& g_0\end{array}\right]& \left(33\right)\end{array}$ $\begin{array}{cc}{G}_N^{-1}=\left[\begin{array}{cccccc}{\alpha }_0& \dots & {\alpha }_m& 0& \dots & {\alpha }_{N-1}\\ 0& {\alpha }_0& \dots & {\alpha }_m& 0& 0\\ 0& 0& {\alpha }_0& \dots & {\alpha }_m& 0\\ 0& 0& 0& {\alpha }_0& \dots & {\alpha }_m\\ 0& 0& 0& 0& {\alpha }_0& \dots \\ 0& 0& 0& 0& 0& {\alpha }_0\end{array}\right]& \left(34\right)\end{array}$

This inversion may be proven by induction. Note that ₀=_m=1, and α₀=1 since G_N is full-rank.

This result holds for N=2. For example, with

$G_2=\left[\begin{array}{cc}1& g_1\\ 0& 1\end{array}\right],$

Equation (35) may be determined.

$\begin{array}{cc}{G}_2^{-1}=\left[\begin{array}{cc}1& {\alpha }_1\\ 0& 1\end{array}\right]\mathrm{where}{\alpha }_1=g_1.& \left(35\right)\end{array}$

I may be assumed that the result holds for N and it may be proven that the result also holds for N+1, as shown in Equations (36) and (37) below.

$\begin{array}{cc}{G}_{N+1}=\left[\begin{array}{cc}{G}_N& \left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]\\ 0& g_0\end{array}\right]& \left(36\right)\end{array}$ $\begin{array}{cc}{G}_N=\left[\begin{array}{cccccc}{g}_0& \dots & g_m& 0& \dots & 0\\ 0& g_0& \dots & g_m& 0& 0\\ 0& 0& g_0& \dots & g_m& 0\\ 0& 0& 0& g_0& \dots & g_m\\ 0& 0& 0& 0& g_0& \dots \\ 0& 0& 0& 0& 0& g_0\end{array}\right]& \left(37\right)\end{array}$

The inverse of G_N+1 may be written as Equation (38) below.

$\begin{array}{cc}{G}_{N+1}^{-1}=\left[\begin{array}{cc}{B}_N& c\\ 0& d\end{array}\right]& \left(38\right)\end{array}$

The goal is to find B_N,c and d. Since G_N+1⁻¹G_N+1=I_N+1, this results in Equation (39) below.

$\begin{array}{cc}\left[\begin{array}{cc}{B}_N& c\\ 0& d\end{array}\right]\left[\begin{array}{cc}{G}_N& \left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]\\ 0& g_0\end{array}\right]=I_{N+1}& \left(39\right)\end{array}$

This results in Equation (40), (41), and (42), given that ₀ 1.

$\begin{array}{cc}{B}_N{G}_N=I_N\to B_N=G_N^{-1}& \left(40\right)\end{array}$ $\begin{array}{cc}{B}_N\left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]+c=0_{N\times 1}\to c=G_N^{-1}\left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]& \left(41\right)\end{array}$ $\begin{array}{cc}d{g}_0=1\to d=1={\alpha }_0& \left(42\right)\end{array}$

From Equations (40)-(42), this results in Equation (43) below.

$\begin{array}{cc}{G}_{N+1}^{-1}=\left[\begin{array}{cc}{G}_N^{-1}& G_N^{-1}\left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]\\ 0& {\alpha }_0\end{array}\right]=\left[\begin{array}{c}\left[\begin{array}{cccccc}{\alpha }_0& \dots & {\alpha }_m& 0& \dots & {\alpha }_{N-1}\\ 0& {\alpha }_0& \dots & {\alpha }_m& 0& ⋮\\ 0& 0& {\alpha }_0& \dots & {\alpha }_m& 0\\ 0& 0& 0& {\alpha }_0& \dots & {\alpha }_m\\ 0& 0& 0& 0& {\alpha }_0& \dots \\ 0& 0& 0& 0& 0& {\alpha }_0\end{array}\right]\\ 0\end{array}\begin{array}{c}\left[\begin{array}{cccccc}{\alpha }_0& \dots & {\alpha }_m& 0& \dots & {\alpha }_{N-1}\\ 0& {\alpha }_0& \dots & {\alpha }_m& 0& ⋮\\ 0& 0& {\alpha }_0& \dots & {\alpha }_m& 0\\ 0& 0& 0& {\alpha }_0& \dots & {\alpha }_m\\ 0& 0& 0& 0& {\alpha }_0& \dots \\ 0& 0& 0& 0& 0& {\alpha }_0\end{array}\right]\\ {\alpha }_0\end{array}\left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]\right]& \left(43\right)\end{array}$

where α₀=1. To complete the proof, it suffices to show Equation (44) below.

$\begin{array}{cc}c=\left[\begin{array}{c}{c}_1\\ c_2\\ ⋮\\ c_N\end{array}\right]=\left[\begin{array}{cccccc}{\alpha }_0& \dots & {\alpha }_m& 0& \dots & {\alpha }_{N-1}\\ 0& {\alpha }_0& \dots & {\alpha }_m& 0& ⋮\\ 0& 0& {\alpha }_0& \dots & {\alpha }_m& 0\\ 0& 0& 0& {\alpha }_0& \dots & {\alpha }_m\\ 0& 0& 0& 0& {\alpha }_0& \dots \\ 0& 0& 0& 0& 0& {\alpha }_0\end{array}\right]\left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]=\left[\begin{array}{c}{\alpha }_N\\ {\alpha }_{N-1}\\ ⋮\\ {\alpha }_1\end{array}\right]& \left(44\right)\end{array}$

For any α_N, it may be determined that c_j=α_N−j+1 for 2≤j≤N, resulting in Equation (45) below.

$\begin{array}{cc}{c}_j=\left[0,{\alpha }_0,\dots ,{\alpha }_{N-j}\right]\left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]& \left(45\right)\end{array}$

From G_N⁻¹G_N I_N (considering the first N−1 rows), Equations (46) results in Equation (47) below.

$\begin{array}{cc}\left[0,{\alpha }_0,\dots ,{\alpha }_{N-j+1}\right]\left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\\ g_0\end{array}\right]=0,\mathrm{for}2\le j\le N& \left(46\right)\end{array}$ $\begin{array}{cc}\left[0,{\alpha }_0,\dots ,{\alpha }_{N-j}\right]\left[\begin{array}{c}0\\ g_m\\ ⋮\\ g_1\end{array}\right]+{\alpha }_{N-j+1}{g}_0=0& \left(47\right)\end{array}$

Alternatively, this results in Equation (48) below.

$\begin{array}{cc}{c}_j+{\alpha }_{N-j+1}=0\to c_j={\alpha }_{N-j+1}\mathrm{for}2\le j\le N& \left(48\right)\end{array}$

The inverse CC generator polynomial for different special node lengths may be nested. Equation (49) is shown below for length 2, 4, 8 16 rate-1 special nodes.

$G_{\mathrm{inv},\mathrm{CC}}=\left[\begin{array}{ccccccccccccccc}1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0\\ 1& 0& 1& 1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0\\ 1& 0& 1& 1& 1& 1& 1& 1& 0& 0& 0& 0& 0& 0& 0\\ 1& 0& 1& 1& 1& 1& 1& 1& 0& 0& 1& 0& 1& 0& 1\end{array}\right]$

A CC generator and inverse generator matrix of length N=2ⁿ special node may take the form shown in Equations (50) and (51) below.

$\begin{array}{cc}{G}_{\mathrm{CC},n}=\left[\begin{array}{cccccc}{g}_0& \dots & g_m& 0& \dots & 0\\ 0& g_0& \dots & g_m& 0& 0\\ 0& 0& g_0& \dots & g_m& 0\\ 0& 0& 0& g_0& \dots & g_m\\ 0& 0& 0& 0& g_0& \dots \\ 0& 0& 0& 0& 0& g_0\end{array}\right]& \left(50\right)\end{array}$ $\begin{array}{cc}{G}_{\mathrm{CC},n}^{-1}=\left[\begin{array}{cccccc}{\alpha }_0& \dots & {\alpha }_m& 0& \dots & {\alpha }_{N-1}\\ 0& {\alpha }_0& \dots & {\alpha }_m& 0& ⋮\\ 0& 0& {\alpha }_0& \dots & {\alpha }_m& 0\\ 0& 0& 0& {\alpha }_0& \dots & {\alpha }_m\\ 0& 0& 0& 0& {\alpha }_0& \dots \\ 0& 0& 0& 0& 0& {\alpha }_0\end{array}\right]& \left(51\right)\end{array}$

The generator polynomial and inverse generator polynomial may be (₀, . . . , _m) and (α₀, . . . , α_N−1), respectively. G_CC,n+1⁻¹ may be calculated and the first N elements of the first row may be equal to the first row of G_CC,n⁻¹, as shown in Equation (52) below.

$\begin{array}{cc}{G}_{\mathrm{CC},n+1}=\left[\begin{array}{cc}{G}_{\mathrm{CC},n}& A\\ 0& G_{\mathrm{CC},n}\end{array}\right]& \left(52\right)\end{array}$

G_CC,n+1⁻¹ may take the form shown in Equation (53) below.

$\begin{array}{cc}{G}_{\mathrm{CC},n+1}^{-1}=\left[\begin{array}{cc}B& C\\ 0& D\end{array}\right]& \left(53\right)\end{array}$

B may be calculated and compared with G_CC,n⁻¹. I_n may be set to the identity matrix of size 2ⁿ×2ⁿ, resulting in Equation (54) or (55) below.

$\begin{array}{cc}{G}_{\mathrm{CC},n+1}^{-1}·G_{CC,n+1}=I_{n+1}\to \left[\begin{array}{cc}B& C\\ 0& D\end{array}\right]\left[\begin{array}{cc}{G}_{\mathrm{CC},n}& A\\ 0& G_{\mathrm{CC},n}\end{array}\right]=\left[\begin{array}{cc}{I}_n& 0\\ 0& I_n\end{array}\right]& \left(54\right)\end{array}$ $\begin{array}{cc}\left[\begin{array}{cc}B·G_{\mathrm{CC},n}& B·A+C·G_{\mathrm{CC},n}\\ 0& D·G_{\mathrm{CC},n}\end{array}\right]=\left[\begin{array}{cc}{I}_n& 0\\ 0& I_n\end{array}\right]& \left(55\right)\end{array}$

This results in Equation (56) below.

$\begin{array}{cc}B·G_{\mathrm{CC},n}=I_n& \left(56\right)\end{array}$

This may be alternatively set forth as B=G_CC,n⁻¹ which means that the first row of B is equal to the first row of G_CC,n⁻¹, i.e., (α₀ . . . , α_N−1). Therefore, the first N elements of the first row of G_CC,n+1⁻¹ are equal to the first row of G_CC,n⁻¹, and this proves the nested property of inverse CC generator polynomial.

With the above property, one inverse shift registers of length N=2ⁿ may be sufficient for the PAC decoder inverse CC operations. When operating at a given special node of length M, only the first M memory elements of the shift register may be taken (e.g., the first L≤elements where L is the position of the last “1” in the inverse polynomial).

FIG. 5 is a flowchart illustrating a method of SSCL decoding of a PAC code, according to an embodiment.

At 502, a receiver of an electronic device receives a channel encoded with a PAC code. At 504, a decoder of the electronic device performs SSCL decoding on the channel via a decoding tree to generate a decoded codeword. The decoding tree includes a special node that generates candidate codeword output based on predefined processing using CC state input and channel vector input, without processing a sub-tree of the special node. The special node may be a rate-0 node, a repetition node, a rate-1 node, and an SPC node, and the predefined processing is described in detail above.

FIG. 6 is a block diagram of an electronic device in a network environment 600, according to an embodiment.

Referring to FIG. 6, an electronic device 601 in a network environment 600 may communicate with an electronic device 602 via a first network 698 (e.g., a short-range wireless communication network), or an electronic device 604 or a server 608 via a second network 699 (e.g., a long-range wireless communication network). The electronic device 601 may communicate with the electronic device 604 via the server 608. The electronic device 601 may include a processor 620, a memory 630, an input device 650, a sound output device 655, a display device 660, an audio module 670, a sensor module 676, an interface 677, a haptic module 679, a camera module 680, a power management module 688, a battery 689, a communication module 690, a subscriber identification module (SIM) card 696, or an antenna module 697. In one embodiment, at least one (e.g., the display device 660 or the camera module 680) of the components may be omitted from the electronic device 601, or one or more other components may be added to the electronic device 601. Some of the components may be implemented as a single integrated circuit (IC). For example, the sensor module 676 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device 660 (e.g., a display).

The processor 620 may execute software (e.g., a program 640) to control at least one other component (e.g., a hardware or a software component) of the electronic device 601 coupled with the processor 620 and may perform various data processing or computations.

As at least part of the data processing or computations, the processor 620 may load a command or data received from another component (e.g., the sensor module 676 or the communication module 690) in volatile memory 632, process the command or the data stored in the volatile memory 632, and store resulting data in non-volatile memory 634. The processor 620 may include a main processor 621 (e.g., a central processing unit (CPU) or an application processor (AP)), and an auxiliary processor 623 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operable independently from, or in conjunction with, the main processor 621. Additionally or alternatively, the auxiliary processor 623 may be adapted to consume less power than the main processor 621, or execute a particular function. The auxiliary processor 623 may be implemented as being separate from, or a part of, the main processor 621.

The auxiliary processor 623 may control at least some of the functions or states related to at least one component (e.g., the display device 660, the sensor module 676, or the communication module 690) among the components of the electronic device 601, instead of the main processor 621 while the main processor 621 is in an inactive (e.g., sleep) state, or together with the main processor 621 while the main processor 621 is in an active state (e.g., executing an application). The auxiliary processor 623 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 680 or the communication module 690) functionally related to the auxiliary processor 623.

The memory 630 may store various data used by at least one component (e.g., the processor 620 or the sensor module 676) of the electronic device 601. The various data may include, for example, software (e.g., the program 640) and input data or output data for a command related thereto. The memory 630 may include the volatile memory 632 or the non-volatile memory 634. Non-volatile memory 634 may include internal memory 636 and/or external memory 638.

The program 640 may be stored in the memory 630 as software, and may include, for example, an operating system (OS) 642, middleware 644, or an application 646.

The input device 650 may receive a command or data to be used by another component (e.g., the processor 620) of the electronic device 601, from the outside (e.g., a user) of the electronic device 601. The input device 650 may include, for example, a microphone, a mouse, or a keyboard.

The sound output device 655 may output sound signals to the outside of the electronic device 601. The sound output device 655 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or recording, and the receiver may be used for receiving an incoming call. The receiver may be implemented as being separate from, or a part of, the speaker.

The display device 660 may visually provide information to the outside (e.g., a user) of the electronic device 601. The display device 660 may include, for example, a display, a hologram device, or a projector and control circuitry to control a corresponding one of the display, hologram device, and projector. The display device 660 may include touch circuitry adapted to detect a touch, or sensor circuitry (e.g., a pressure sensor) adapted to measure the intensity of force incurred by the touch.

The audio module 670 may convert a sound into an electrical signal and vice versa. The audio module 670 may obtain the sound via the input device 650 or output the sound via the sound output device 655 or a headphone of an external electronic device 602 directly (e.g., wired) or wirelessly coupled with the electronic device 601.

The sensor module 676 may detect an operational state (e.g., power or temperature) of the electronic device 601 or an environmental state (e.g., a state of a user) external to the electronic device 601, and then generate an electrical signal or data value corresponding to the detected state. The sensor module 676 may include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

The interface 677 may support one or more specified protocols to be used for the electronic device 601 to be coupled with the external electronic device 602 directly (e.g., wired) or wirelessly. The interface 677 may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

A connecting terminal 678 may include a connector via which the electronic device 601 may be physically connected with the external electronic device 602. The connecting terminal 678 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

The haptic module 679 may convert an electrical signal into a mechanical stimulus (e.g., a vibration or a movement) or an electrical stimulus which may be recognized by a user via tactile sensation or kinesthetic sensation. The haptic module 679 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

The camera module 680 may capture a still image or moving images. The camera module 680 may include one or more lenses, image sensors, image signal processors, or flashes. The power management module 688 may manage power supplied to the electronic device 601. The power management module 688 may be implemented as at least part of, for example, a power management integrated circuit (PMIC).

The battery 689 may supply power to at least one component of the electronic device 601. The battery 689 may include, for example, a primary cell which is not rechargeable, a secondary cell which is rechargeable, or a fuel cell.

The communication module 690 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 601 and the external electronic device (e.g., the electronic device 602, the electronic device 604, or the server 608) and performing communication via the established communication channel. The communication module 690 may include one or more communication processors that are operable independently from the processor 620 (e.g., the AP) and supports a direct (e.g., wired) communication or a wireless communication. The communication module 690 may include a wireless communication module 692 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 694 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules may communicate with the external electronic device via the first network 698 (e.g., a short-range communication network, such as BLUETOOTH™, wireless-fidelity (Wi-Fi) direct, or a standard of the Infrared Data Association (IrDA)) or the second network 699 (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., LAN or wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single IC), or may be implemented as multiple components (e.g., multiple ICs) that are separate from each other. The wireless communication module 692 may identify and authenticate the electronic device 601 in a communication network, such as the first network 698 or the second network 699, using subscriber information (e.g., international mobile subscriber identity (IMSI)) stored in the subscriber identification module 696.

The antenna module 697 may transmit or receive a signal or power to or from the outside (e.g., the external electronic device) of the electronic device 601. The antenna module 697 may include one or more antennas, and, therefrom, at least one antenna appropriate for a communication scheme used in the communication network, such as the first network 698 or the second network 699, may be selected, for example, by the communication module 690 (e.g., the wireless communication module 692). The signal or the power may then be transmitted or received between the communication module 690 and the external electronic device via the selected at least one antenna.

Commands or data may be transmitted or received between the electronic device 601 and the external electronic device 604 via the server 608 coupled with the second network 699. Each of the electronic devices 602 and 604 may be a device of a same type as, or a different type, from the electronic device 601. All or some of operations to be executed at the electronic device 601 may be executed at one or more of the external electronic devices 602, 604, or 608. For example, if the electronic device 601 should perform a function or a service automatically, or in response to a request from a user or another device, the electronic device 601, instead of, or in addition to, executing the function or the service, may request the one or more external electronic devices to perform at least part of the function or the service. The one or more external electronic devices receiving the request may perform the at least part of the function or the service requested, or an additional function or an additional service related to the request and transfer an outcome of the performing to the electronic device 601. The electronic device 601 may provide the outcome, with or without further processing of the outcome, as at least part of a reply to the request. To that end, a cloud computing, distributed computing, or client-server computing technology may be used, for example.

Embodiments of the subject matter and the operations described in this specification may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer-program instructions, encoded on computer-storage medium for execution by, or to control the operation of data-processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. A computer-storage medium can be, or be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial-access memory array or device, or a combination thereof. Moreover, while a computer-storage medium is not a propagated signal, a computer-storage medium may be a source or destination of computer-program instructions encoded in an artificially-generated propagated signal. The computer-storage medium can also be, or be included in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Additionally, the operations described in this specification may be implemented as operations performed by a data-processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

While this specification may contain many specific implementation details, the implementation details should not be construed as limitations on the scope of any claimed subject matter, but rather be construed as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Thus, particular embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

As will be recognized by those skilled in the art, the innovative concepts described herein may be modified and varied over a wide range of applications. Accordingly, the scope of claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is instead defined by the following claims.

Claims

1. A method comprising: receiving, at an electronic device, a channel encoded with a polarization-adjusted convolutional (PAC) code; andgenerating a decoded codeword, wherein the decoded codeword is generated based at least in part on simplified successive cancellation list (SSCL) decoding performed, by the electronic device, on the channel via a decoding tree, wherein the decoding tree comprises a node that generates candidate codeword output based on predefined processing using convolutional code (CC) state input and channel vector input, and wherein a sub-tree of the node remains unprocessed.

2. The method of claim 1, wherein: the node comprises a rate-0 node, and each leaf node of the sub-tree comprises a zero-valued bit; andthe candidate codeword output comprises a constant codeword for each member of a list in the SSCL decoding.

3. The method of claim 1, wherein: the node comprises a repetition node, a last leaf node of the sub-tree comprises a one-valued bit, and remaining leaf nodes of the sub-tree comprise zero-valued bits; andthe candidate codeword output comprises one of two constant codewords for each member of a list in the SSCL decoding.

4. The method of claim 1, wherein: the node comprises a rate-1 node, and each leaf node of the sub-tree comprises a one-valued bit; andthe candidate codeword output is generated based on a determination of an information-carrier vector from a CC codeword.

5. The method of claim 4, wherein the candidate codeword output is based on a non-linear code.

6. The method of claim 1, wherein: the node comprises a single parity check (SPC) node, a first leaf node of the sub-tree comprises a zero-valued bit, and remaining leaf nodes of the sub-tree comprise one-valued bits; andthe candidate codeword output is generated based on a least likelihood ratio (LLR) scrambling and a determination of an information-carrier vector from a CC codeword.

7. The method of claim 6, wherein the candidate codeword output is generated based on an SPC codebook.

8. The method of claim 1, further comprising applying inverse CC encoding for different lengths of the node.

9. The method of claim 1, wherein the node further generates CC state output, an information-carrier vector, and a CC codeword corresponding to the information-carrier vector.

10. The method of claim 1, wherein the SSCL decoding is performed with parallel successive cancellation (SC) decoders, a first list is maintained for an information-carrier vector, and a second list is maintained for a CC codeword.

11. The method of claim 1, wherein the channel vector input comprises an LLR vector.

12. An electronic device comprising: a receiver configured to receive a channel encoded with a polarization-adjusted convolutional (PAC) code; anda decoder configured to generate a decoded codeword, wherein the decoded codeword is generated based at least in part on simplified successive cancellation list (SSCL) decoding performed on the channel via a decoding tree, wherein the decoding tree comprises a node that generates candidate codeword output based on predefined processing using convolutional code (CC) state input and channel vector input, and wherein a sub-tree of the node remains unprocessed.

13. The electronic device of claim 12, wherein: the node comprises a rate-0 node, and each leaf node of the sub-tree comprises a zero-valued bit; andthe candidate codeword output comprises a constant codeword for each member of a list in the SSCL decoding.

14. The electronic device of claim 12, wherein: the node comprises a repetition node, a last leaf node of the sub-tree comprises a one-valued bit, and remaining leaf nodes of the sub-tree comprise zero-valued bits; andthe candidate codeword output comprises one of two constant codewords for each member of a list in the SSCL decoding.

15. The electronic device of claim 12, wherein: the node comprises a rate-1 node, and each leaf node of the sub-tree comprises a one-valued bit; andthe candidate codeword output is generated based on a determination of an information-carrier vector from a CC codeword.

16. The electronic device of claim 15, wherein the candidate codeword output is based on a non-linear code.

17. The electronic device of claim 12, wherein: the node comprises a single parity check (SPC) node, a first leaf node of the sub-tree comprises a zero-valued bit, and remaining leaf nodes of the sub-tree comprise one-valued bits; andthe candidate codeword output is generated based on a least likelihood ratio (LLR) scrambling and a determination of an information-carrier vector from a CC codeword.

18. The electronic device of claim 12, wherein the decoder is further configured to apply inverse CC encoding for different lengths of the node.

19. The electronic device of claim 12, wherein the node further generates CC state output, an information-carrier vector, and a CC codeword corresponding to the information-carrier vector.

20. An electronic device comprising: a processor; anda non-transitory computer readable storage medium storing instructions that, when executed, cause the processor to: receive a channel encoded with a polarization-adjusted convolutional (PAC) code; andgenerate a decoded codeword, wherein the decoded codeword is generated based at least in part on simplified successive cancellation list (SSCL) decoding performed on the channel via a decoding tree, wherein the decoding tree comprises a node that generates candidate codeword output based on predefined processing using convolutional code (CC) state input and channel vector input, and wherein a sub-tree of the node remains unprocessed.