Monitoring and detecting fails of static signals on I/O pins of a semiconductor circuit
A large number of I/O pins of a computer chip are used to provide signals for the chips maintenance and infrastructure and are not used for functional use or for traffic flow. Most of these signals either specify a static setting or are used in functions which are only needed in the initialization of the chip. During functional operation mode of the chip, all these signals are supposed to remain at a static value. However, sometimes, the development of shorts and opens or other fail mechanisms such as the injection of noise by induction will cause the signal integrity to be compromised despite all prior verification and signal noise analysis.
The invention comprises a method and apparatus for monitoring and detecting errors occurring on the input/output (I/O) pins of an integrated circuit.
An exemplary embodiment of the invention presents a method for detecting failures on static pervasive signals applied to I/O pins of an integrated circuit. The method comprises the grouping of the static pervasive signals into one or more groups, building a signal signature for each of the one or more groups, feeding each of the signal signatures of the one or more groups into a store element and comparing each of the signal signatures for the one or more groups with the output of the store element into which it is fed. If there is an error such that the static pervasive signal is changed, a signature mismatch for each of the signal signatures that differs from the output of the store element into which it is fed is created and presented as an error indicator output.
An exemplary embodiment of a logical implementation of the present invention is represented for each group of I/O pins as follows. The group of two or more I/O pins has each pin feeding its signal into a separate receiver circuit. The output of each receiver, in turn, is fed into a signal signature circuit. An example of such a signal signature circuit would be an exclusive or (XOR) circuit. The single output of the signal signature circuit is then fed into a storage element. An example of a storage element is a latch circuit. The output of the storage element and the output of the signal signature circuit are fed into a compare circuit. The results at the output of the compare circuit are then fed into capture logic where it is retained as an error or non-error indicator.
FIG. 1—Represents an overview of an exemplary embodiment of the invention showing the signal flow of groups of I/O pins with static pervasive signals to be monitored for the development of errors.
FIG. 2—Represents an exemplary embodiment of a group of I/O pins with static pervasive signals with a logic block diagram from the I/O to error capture.
The signal signatures are then each fed into a separate storage element 7. Each signal signature coming into the storage element is compared to the signal signature at the output of the storage element by compare circuits 8. If a signal mismatch occurs as a result of the compare, the mismatch is indicated and held by the mismatch circuits 9. The mismatch circuits 9 may then be interrogated at outputs 10, 11, and 12.
The circuit arrangement and composition may be different from that exemplified above. For example, the gating function may occur after the signal signature function. Also, the I/O identified above may not only be external I/O but may be internal to the chip. The capture circuit fed by line 29 is not shown as this is typically part of the processor chip circuitry.