Patent Grant
7670880
The present invention relates generally to semiconductor processing techniques. More particularly, the invention includes a method and structure for forming an integrated spatial light modulator. Merely by way of example, the invention has been applied to a method of forming standoff structures present in a bonded substrate structure. The method and structure can be applied to other applications as well, such as actuators, sensors, detectors, and display components.
Spatial light modulators (SLMs) have numerous applications in the areas of optical information processing, projection displays, video and graphics monitors, and televisions. Reflective SLMs are devices that modulate incident light in a spatial pattern to reflect an image corresponding to an electrical or optical input. The incident light may be modulated in phase, intensity, polarization, or deflection direction. A reflective SLM is typically comprised of a one or two-dimensional array of addressable picture elements (pixels) capable of reflecting incident light. Source pixel data is first processes by an associated control circuit, then loaded into the pixel array, one frame at a time.
The fabrication processes used to manufacture SLMs are varied. In some of the fabrication processes, multiple substrates are bonded together to form the SLM structure. Some of these fabrication processes require alignment of the substrates with tolerances on the order of microns prior to bonding, which may be a time consuming and expensive process.
Therefore there is a need in the art for improved methods and structures for integrated SLMs.
According to the present invention semiconductor processing techniques are provided. More particularly, the invention includes a method and structure for forming an integrated spatial light modulator. Merely by way of example, the invention has been applied to a method of forming standoff structures present in a bonded substrate structure. The method and structure can be applied to other applications as well, such as actuators, sensors, detectors, and display components.
In a specific embodiment of the present invention, a method of fabricating an integrated spatial light modulator is provided. The method comprises providing a first substrate including a bonding surface, processing a device substrate to form at least an electrode layer, the electrode layer including a plurality of electrodes, and depositing a standoff layer on the electrode layer. The method also comprises forming standoff structures from the standoff layer and joining the bonding surface of the first substrate to the standoff structures on the device substrate.
In another specific embodiment of the present invention, a method of fabricating an integrated spatial light modulator is provided. The method comprises providing a first substrate including a bonding surface, providing a second substrate including a plurality of electrodes, and depositing a standoff layer on the second substrate. The method also comprises forming standoff structures from the standoff layer, joining the bonding surface of the first substrate to the standoff structures on the second substrate, and thinning the first substrate. The method further comprises patterning the first substrate to form a mask; and forming a plurality of moveable structures from the first substrate, at least one of the moveable structures aligned with at least one of the plurality of electrodes.
In yet another specific embodiment of the present invention, an array of integrated spatial light modulators is provided. The array of integrated spatial light modulators comprises an electrode layer coupled to a device substrate, the electrode layer including a plurality of electrodes and at least one alignment mark, and a three-dimensional standoff structure, the standoff structure having side regions defined in a plane parallel to the device substrate, bottom regions coupled to the device substrate, and top regions opposite the bottom regions. The apparatus further comprises a semi-transparent silicon layer coupled to the top regions of the standoff structure, the semi-transparent silicon layer comprising a hinge support region coupled to the top regions of the standoff structure, a plurality of hinges coupled to the hinge support regions, and a plurality of moveable members aligned with respect to the at least one alignment mark by imaging the at least one alignment mark through the semi-transparent silicon layer.
Numerous benefits are achieved using the present invention over conventional techniques. For example, in an embodiment according to the present invention, the alignment tolerances used during the substrate bonding process are greatly relaxed. Moreover, the dimensions of the composite substrate used in one embodiment are reduced, decreasing cost and improving layer uniformity. This increased layer uniformity extends, for example, to the thickness of a micro-mirror layer present in the composite substrate. Additionally, standoffs fabricated according to embodiments of the present invention provide a bonding surface with decrease surface roughness, leading to an increase in bond strength. Depending upon the embodiment, one or more of these benefits may exist. These and other benefits have been described throughout the present specification and more particularly below.
Various additional objects, features and advantages of the present invention can be more fully appreciated with reference to the detailed description and accompanying drawings that follow.
According to the present invention semiconductor processing techniques are provided. More particularly, the invention includes a method and structure for forming an integrated spatial light modulator. Merely by way of example, the invention has been applied to a method of forming standoff structures present in a bonded substrate structure. The method and structure can be applied to other applications as well, such as actuators, sensors, detectors, and display components.
Layer 114 of the SOI substrate is processed using semiconductor processing techniques to form support members 116, which extend from the surface of the layer 114. Masking and etching processes well known to those of skill in the art are utilized to form support members 116. In a typical process, the depth 130 of the etch step defines the height of the support members while the lateral dimensions of the masking layer define the two-dimensional profile of the support members. The surface morphology at surface 132 is a function of the etch process and is typically selected to provide a smooth surface with a uniform etch depth. Although the support members 116 are illustrated in only one dimension in the figure, they typically form two-dimensional structures, defining recessed regions 118 surrounded by support members 116. Support members fabricated from a layer of single crystal silicon provide a degree of mechanical rigidity to the composite structure and are processed using well developed semiconductor processing techniques.
The electrode substrate 105 can be an integrated circuit device having a plurality of electrode devices 122, as shown. The integrated circuit device can include drive devices coupled to each of the electrodes (not shown). In one application, the drive devices include CMOS circuitry fabricated in processing steps (not shown) prior to the formation of the plurality of electrode devices 122. The drive devices can be used to apply voltages to the electrodes to actuate selected mirror devices present on the SOI substrate structure. Preferably, the electrode substrate structure is made using a silicon wafer or other like substrate material. Further details of both the SOI and electrode substrate structures can be found in U.S. Pat. No. 7,118,234, filed Jan. 13, 2004, commonly assigned, and hereby incorporated by reference for all purposes.
In some applications, substrates 100 and 105 are joined to form a composite substrate structure. Wafer bonding techniques are utilized to join the substrates and form a mechanical bond. Support members 116 extending from the lower surface of substrate 100 are bonded to the upper surface of the electrode substrate at locations 120. For example, support members fabricated from silicon may form a hermetic seal when bonded to silicon areas present on the upper surface of a silicon electrode substrate. Recessed regions 118 will form cavities above the electrodes 122 after the bonding process. After bonding, substrate 100 is thinned using chemical mechanical polishing (CMP), grinding, etchback, any combination of these, and the like. In one application, the buried oxide layer 112 provides an etch stop layer during the thinning process. After exposure of layer 114, mirror structures are patterned and fabricated in layer 114 as described above.
As illustrated in
As illustrated in
Device substrate 205 includes a number of layers, of which only a selected few are illustrated in
To provide a vertical clearance between electrodes 222 and layer 214, in which micro-mirrors are formed in one embodiment, standoff structures 220 are formed on the surface of substrate 205. In embodiments according to the present invention, the standoff structures have predetermined dimensions. In an embodiment according to the present invention, the height of the standoff structure is 1.9 μm. Alternatively, the height ranges from about 0.5 μm to about 2.5 μm in other embodiments. Of course, the height will depend upon the particular applications. Additionally, the lateral dimensions of the standoff structures are predetermined. In the embodiment illustrated in
The dimensions of the standoff structures in some embodiments are defined in relation to the dimensions of the micro-mirrors formed in layer 214. For example, in a specific embodiment, the tilt angle of the micro-mirrors in an activated state is 12°. Therefore, the width, length, and depth of the micro-mirrors, along with the relationship of the micro-mirrors to the hinges upon which the micro-mirrors rotate, may be used as inputs in the determination of the standoff structure dimensions. Merely by way of example, for square micro-mirrors with diagonal hinges running from corner to corner, the distance from the center of the micro-mirror to the corner of the micro-mirror will define the hypotenuse of a right triangle. The tilt angle of 12° will define the angle between the bottom of the right triangle and the hypotenuse. Thus, one may calculate the minimum height of the standoff structure for which contact is made between the corner of the micro-mirror and substrate 205 when the micro-mirror is in the activated state. Of course, electrodes extending above the surface of substrate 205, along with other device features, will impact the calculation process and the results produced.
As illustrated in the
Moreover, in some embodiments of the present invention, the process used to deposit the layer or layers from which the standoff structures are fabricated is performed in light of the structures present on the device substrate. For example, some CMOS circuitry may be adversely impacted by performing high temperature deposition processes, as these high temperature deposition processes may damage metals or result in diffusion of junctions associated with the CMOS circuitry. Thus, in a particular embodiment of the present invention, low temperature deposition, patterning, and etching processes, such as processes performed at temperatures of less than 500° C., are used to form the layer from which the standoff structures are fabricated. In another specific embodiment, deposition, patterning, and etching processes performed at less than 400° C., are used to form the layer from which the standoff structures are fabricated.
The deposited layer 310 has a predetermined thickness t1 as initially deposited. In a specific embodiment, the thickness t1 is 2.6 μm. In other embodiments, the thickness ranges from about 1.0 μm to about 3.0 μm. Of course, the thickness will depend on the particular applications. As illustrated in
To planarize the upper surface 312 of the deposited layer 310, an optional CMP step is performed in an embodiment of the present invention. The results produced by the CMP process are illustrated by dashed line 314 in
Embodiments of the present invention in which the standoff regions are fabricated from silicon oxide, silicon nitride, or silicon oxynitride, or combinations thereof, provide benefits based on the electrical and thermal properties of the standoff region material. For example, these materials, among others, provide a high degree of electrical insulation, electrically isolating the device substrate from the mirror layer 214. Moreover, the thermal properties of the material used to deposit the standoff layer, such as thermal insulation, are provided by some embodiments. Merely by way of example, light absorbed by micro-mirrors fabricated in layer 214 may increase the temperature of the micro-mirrors. Thus, for instance, a thermally insulating standoff region will reduce the conduction of heat from the micro-mirrors to the device substrate. Other suitable standoff regions materials, such as polysilicon material, including amorphous polysilicon are characterized by electrical and thermal properties that provide benefits in alternative embodiments.
As illustrated in
As discussed above, in some embodiments of the present invention, the processes used to deposit, pattern, and etch the layer or layers from which the standoff structures are fabricated are performed at low temperatures. For example, these processing steps may be performed with a view to the structures present on the device substrate prior to the formation of the standoff structures, such as CMOS circuitry. Since some CMOS circuitry may be adversely impacted by performing high temperature deposition processes, which may damage metals coupling CMOS transistors or result in diffusion of junctions associated with the CMOS circuitry, low temperature deposition processes are utilized according to some embodiments of the present invention. Moreover, in a particular embodiment of the present invention, low temperature deposition, patterning, and etching processes, such as processes performed at temperatures of less than 500° C., are used to form the layer or layers from which the standoff structures are fabricated. In another specific embodiment, deposition, patterning, and etching processes performed at less than 400° C., are used to form the layer from which the standoff structures are fabricated. One of ordinary skill in the art would recognize many variations, modifications, and alternatives within the scope of low temperature processes.
Because the standoff regions and the electrodes are formed on substrate 205, the alignment tolerances for the wafer bonding process are greatly relaxed in comparison to the tolerances present using the structure illustrated in
As illustrated in
In step 406, a standoff layer is deposited on the electrode layer of the device substrate. In a specific embodiment, the standoff layer is a silicon oxide layer as described above. Other standoff layer materials, including silicon nitride, amorphous silicon, and low temperature poly-silicon are utilized in alternative embodiments. In embodiments of the present invention, the formation of the standoff layer is performed using low temperature deposition processes, for example, temperatures less than 500° C. In a particular embodiment according to the present invention, the standoff layer is formed using a deposition process performed at a temperature of less than about 400° C. In these embodiments, the deposition and processing of the standoff layer does not adversely impact the circuitry previously fabricated on the device substrate. The thickness of the standoff layer is a predetermined thickness. In one embodiment, the thickness of the standoff layer as deposited is about 2.0 μm. In alternative embodiments the thickness ranges from about 0.5 μm to about 5.0 μm.
In step 408, a photoresist layer is deposited on the standoff layer. The photoresist layer is patterned in step 410 and subsequent processing steps are used to form an etch mask. The formation of an etch mask will be evident to those of skill in the art. In step 412, the etch mask is used to etch selected portions of the standoff layer to form standoff structures. In a particular embodiment, the etch process is terminated when the electrode layer is exposed. In other embodiments, the etch process is terminated prior to exposure of the electrodes present on the device substrate, providing a passivation layer for the electrodes. The lateral shape of the standoff structures is a function of the etch process used in step 412. In one embodiment, an anisotropic etch is used that provides vertical sidewalls. In another embodiment, a combination of an anisotropic (dry) and an isotropic (wet) etch is used to provide vertical sidewalls over a majority of the standoff structure combined with a chemically etched surface when the etching process is terminated.
In step 414 the bonding surface of the first substrate is joined to the standoff structures located on the device substrate. As discussed above, a variety of wafer bonding techniques are employed in embodiments of the present intention. In a particular embodiment, the bonding process is a room temperature covalent bonding process, forming hermetic bonds at the interface between the standoff structures and the bonding surface of the first substrate.
It should be appreciated that the specific steps illustrated in
In step 506, a standoff layer is deposited on the electrode layer of the device substrate. In a specific embodiment, the standoff layer is a silicon oxide as described above, although this is not required by the present invention. Other standoff layer materials, including silicon nitride, amorphous silicon, and poly-silicon are utilized in alternative embodiments. In some embodiments, a combination of these layers is deposited to form a composite multi-layer standoff structure. The thickness of the standoff layer is a predetermined thickness. In the embodiment illustrated by the process flow in
In step 508, a CMP process is performed to reduce the thickness of the as deposited standoff layer and produce a uniform upper surface for the standoff layer. In one embodiment, the RMS roughness of the upper surface of the standoff layer is about 5 Å after the CMP process is completed. As described above, the CMP process results in extremely smooth bonding surfaces of the standoff structure, enhancing the bond formed in later steps. In a specific embodiment, the CMP process removes an upper portion of the standoff layer, resulting in a standoff layer that is about 1.9 μm in thickness.
In step 510, a photoresist layer is deposited on the standoff layer. The photoresist layer is patterned in step 512 and subsequent processing steps are used to form an etch mask. The formation of an etch mask will be evident to those of skill in the art. In step 514, the etch mask is used to etch the standoff layer to form standoff structures. The etch mask protects the polished surfaces of the standoff structures during the etch process. In a particular embodiment, the etch process is terminated when the electrode layer is exposed. In other embodiments, the etch process is terminated prior to exposure of the electrodes present on the device substrate, providing a passivation layer for the electrodes. The lateral shape of the standoff structures is a function of the etch process used in step 514. In one embodiment, an anisotropic etch is used that provides vertical sidewalls. In another embodiment, a combination of an anisotropic (dry) and an isotropic (wet) etch is used to provide vertical sidewalls over a majority of the standoff structure combined with a chemically etched surface when the etching process is terminated.
In step 516 the bonding surface of the first substrate is joined to the standoff structures located on the device substrate. As discussed above, a variety of wafer bonding techniques are employed, including room temperature covalent bonding, in embodiments of the present intention.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
This application is a continuation of U.S. patent application Ser. No. 11/028,946, filed Jan. 3, 2005, which is hereby incorporated by reference for all purposes.
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| Number | Date | Country | |
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| Child | 11670362 | US |
