Patent Application
20250060545
The subject technology is directed to semiconductor devices and methods of manufacturing.
The process of packaging silicon photonics frequently involves the 3D stacking of Electronic IC (EIC) and Photonic IC (PIC). The PIC is typically equipped with a modulator on the transmitter (Tx) end and photo diodes at the receiver (Rx) end, with multiple channels for both transmission and reception. The PIC generally features a considerably thick bulk silicon, around 700 micrometers.
The modulator's design often includes a transmission line of a specific length and characteristic impedance. Depending on the manufacturing foundry, this transmission line might be unshielded, which can result in the emission of electric and magnetic fields. These fields can penetrate the 3D stack in all three dimensions.
Fields spreading across the X and Y dimensions can potentially be terminated by vias connected to the reference nets. However, in the Z direction, the fields can propagate without restriction within the PIC's bulk silicon, limiting the degree to which grounding can be accomplished in the Z direction.
Furthermore, a metal plate is often used on the PIC's backside for efficient heat dissipation but not electrically grounded. Such a setup can often lead to high levels of electrical coupling or crosstalk between the transmitter and receiver paths. The electromagnetic interference in PIC originates mainly from light transmission components like unshielded transmission lines to light detection components like photodetectors. Due to the lack of appropriate electric shielding, the fields from the transmission lines can be directed towards the highly sensitive photodetectors, thereby intensifying the issue.
A further understanding of the nature and advantages of particular embodiments may be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.
The subject technology is directed to semiconductor devices and methods of manufacturing. In a specific embodiment, a method for shielding electromagnetic interference in silicon photonic integrated circuit is provided. The method includes forming a plurality of vias through bulk silicon substrate from reference nets at the front top to a conductive layer covering backside of the photonic integrate circuit chip. Such an arrangement allows for robust electrical connection and allows the metal heat spreader coupled to the backside to act as robust ground thus terminating the electric and magnetic fields. There are other embodiments as well.
In the following description, for the purposes of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. It will be apparent to one skilled in the art, however, that other embodiments may be practiced without some of these details. Several embodiments are described herein, and while various features are ascribed to different embodiments, it should be appreciated that the features described with respect to one embodiment may be incorporated with other embodiments as well. By the same token, however, no single feature or features of any described embodiment should be considered essential to every embodiment of the invention, as other embodiments of the invention may omit such features.
In an example, the term “circuit board”, including the mentioned “main circuit board” and “sub-sized circuit board”, also known as a printed circuit board (PCB), refer a flat, rigid board made of insulating material, typically fiberglass or plastic, that contains a complex network of metallic pathways, or “traces,” that form the electrical circuitry for various electronic devices. Components such as resistors, capacitors, and integrated circuits are then mounted onto the board, and their leads are soldered onto the corresponding traces to create a functioning electronic circuit. “Main” or “sub-sized” is mainly referring to a lateral size of the circuit board, which is one of focal features of the present disclosure.
When an element is referred to herein as being “connected” or “coupled” to another element, it is to be understood that the elements can be directly connected to the other element or have intervening elements present between the elements. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, it should be understood that no intervening elements are present in the “direct” connection between the elements. However, the existence of a direct connection does not exclude other connections, in which intervening elements may be present. When an element is referred to herein as being “electrically coupled” to another element, it is to be understood that the element can directly connected by an electrical conductor to another element.
When an element is referred to herein as being “disposed” in some manner relative to another element (e.g., disposed on, disposed between, disposed under, disposed adjacent to, or disposed in some other relative manner), it is to be understood that the elements can be directly disposed relative to the other element (e.g., disposed directly on another element), or have intervening elements present between the elements. In contrast, when an element is referred to as being “disposed directly” relative to another element, it should be understood that no intervening elements are present in the “direct” example. However, the existence of a direct disposition does not exclude other examples in which intervening elements may be present.
Similarly, when an element is referred to herein as being “bonded” to another element, it is to be understood that the elements can be directly bonded to the other element (without any intervening elements) or have intervening elements present between the bonded elements. In contrast, when an element is referred to as being “directly bonded” to another element, it should be understood that no intervening elements are present in the “direct” bond between the elements. However, the existence of direct bonding does not exclude other forms of bonding, in which intervening elements may be present.
Likewise, when an element is referred to herein as being a “layer,” it is to be understood that the layer can be a single layer or include multiple layers. For example, a conductive layer or a layer of conductive material may comprise multiple different conductive materials or multiple layers of different conductive materials, and a dielectric layer may comprise multiple dielectric materials or multiple layers of dielectric materials. A “metal layer” or a layer of metal material is merely one type of conductive layer. When a layer is described as being coupled or connected to another layer, it is to be understood that the coupled or connected layers may include intervening elements present between the coupled or connected layers. In contrast, when a layer is referred to as being “directly” connected or coupled to another layer, it should be understood that no intervening elements are present between the layers. However, the existence of directly coupled or connected layers does not exclude other connections in which intervening elements may be present.
Moreover, the terms left, right, frontside, backside, top, bottom, forward, reverse, clockwise and counterclockwise are used for purposes of explanation only and are not limited to any fixed direction or orientation. Rather, they are used merely to indicate relative locations and/or directions between various parts of an object and/or components.
Furthermore, the methods and processes described herein may be described in a particular order for ease of description. However, it should be understood that, unless the context dictates otherwise, intervening processes may take place before and/or after any portion of the described process, and further various procedures may be reordered, added, and/or omitted in accordance with various embodiments.
Unless otherwise indicated, all numbers used herein to express quantities, dimensions, and so forth should be understood as being modified in all instances by the term “about.” In this application, the use of the singular includes the plural unless specifically stated otherwise, and use of the terms “and” and “or” means “and/or” unless otherwise indicated. Moreover, the use of the terms “including” and “having,” as well as other forms, such as “includes,” “included,” “has,” “have,” and “had,” should be considered non-exclusive. Also, terms such as “element” or “component” encompass both elements and components comprising one unit and elements and components that comprise more than one unit, unless specifically stated otherwise.
As used herein, the phrase “at least one of” preceding a series of items, with the term “and” or “or” to separate any of the items, modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase “at least one of” does not require selection of at least one of each item listed; rather, the phrase allows a meaning that includes at least one of any one of the items, and/or at least one of any combination of the items. By way of example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; and/or any combination of A, B, and C. In instances where it is intended that a selection be of “at least one of each of A, B, and C,” or alternatively, “at least one of A, at least one of B, and at least one of C,” it is expressly described as such.
One general aspect of the present disclosure includes an integrated circuit device with electromagnetic shielding to suppress crosstalk interference. The integrated circuit device also includes a printed circuit board (PCB). The device also includes a first circuit on a first substrate which includes a first surface and a second surface, the first surface being coupled to the PCB, the second surface may include a first plurality of contacts coupled to the first circuit. The device also includes a second circuit on a second substrate which includes a third surface and a fourth surface. The second circuit includes at least a first component and a second component and is disposed on the first circuit. The third surface may include a second plurality of contacts coupled to the at least the first component and the second component. The second plurality of contacts is coupled to the first plurality of contacts. The device also includes a layer of conductive material disposed on the fourth surface. The device also includes a metal layer disposed in a dielectric between the first component and the third surface. The device also includes a first plurality of vias extended from the fourth surface through the second substrate to at least partially surround the first component, the first plurality of vias being coupled to the layer of conductive material and the metal layer. The device also includes a second plurality of vias extended from the fourth surface through the second substrate to at least partially surround the second component, the second plurality of vias being coupled to the layer of conductive material and the metal layer.
Implementations may include one or more of the following features. The device where the first component may include at least one of optical transmitter, laser, optical amplifier, and optical modulator. The first plurality of vias and the second plurality of vias may include a via-to-via pitch separation smaller than 1 mm for achieving −125 dB isolation between the first component and the second component from the electromagnetic interference with a characteristic frequency up to 30 GHz. The second component may include at least one photodetector, optical receiver, and optical sensor. The device may include an electrical reference net based on the metal layer with a single ground connection. The metal layer may include a first grounded layer at least partially covering an area of the first component and a second grounded layer at least partially covering an area of the second component, the first grounded layer and the second grounded layer being isolated and having independent ground connections. The device may include a first metal plate disposed on a first portion of the fourth surface coupled to the first plurality of vias and the first grounded layer for shielding the first component, and a second metal plate disposed on a second portion of the fourth surface coupled to the second plurality of vias and the second grounded layer for shielding the second component, the second metal plate being decoupled from the first metal plate. The device may include a barrier layer disposed between the fourth surface and the layer of conductive material. The layer of conductive material may include a layer of Cu or Al or an alloy of Cu and Al or a layer of heavily doped silicon. The device may include a metal plate coupled to the layer of conductive material on the fourth surface and electrically grounded.
Another general aspect includes a method for suppressing electrical coupling in a photonics integrated circuit. The method also includes providing a substrate that may include a first surface and the second surface, the second surface being opposite to the first surface. The method also includes packaging a first photonic component and a second photonic component on the first surface. The first photonic component may include at least a light transmitter, the second photonic component may include at least a light detector. The method also includes forming an electrical reference net based on at least one metal layer positioned in a dielectric, the dielectric at least partially covering the light transmitter and the light detector. The method also includes forming a first plurality of vias from the second surface through the substrate to couple to the electrical reference net, the first plurality of vias being disposed to at least partially surround the light transmitter. The method also includes forming a conductive layer on the second surface of the substrate, the conductive layer being coupled to the first plurality of vias and the electrical reference net to form an electrical shield for the first photonic component.
Implementations may include one or more of the following features. The method also may include forming a second plurality of vias from the second surface through the substrate to couple to the electrical reference net, the second plurality of vias being disposed to at least partially surround the light detector. The method may include forming a second conductive layer on the second surface of the substrate to couple to the second plurality of vias and the electrical reference net to form an electrical shield for the second photonic component. Forming the electrical reference net may include forming a first reference net at least partially covering an area associated with the light transmitter, and forming a second reference net at least partially covering an area associated with the light detector. The first reference net and the second reference net are electrically isolated from each other and separately grounded. The method may include forming at least one first metal contact and at least one second metal contact on the first surface, the at least one first metal contact being arranged to couple to the light transmitter and the at least one second metal contact being arranged to couple to the light detector. The method may include coupling the at least one first metal contact and the at least one second metal contact respectively to corresponding contacts of an electronic integrated circuit.
Yet another general aspect includes a photonics integrated device with electromagnetic shielding. The photonics integrated device also includes a substrate with a first surface and a second surface, the second surface being opposite to the first surface. The device also includes a circuit formed on the first surface. The circuit may include at least a first component and a second component. The first component may include at least a light transmitter. The second component may include at least a light detector. The device also includes a metal layer disposed in a dielectric on the first surface. The dielectric at least partially covers the circuit. The metal layer is used as an electrical reference which is set to have a certain voltage potential level, e.g., 0V. The device also includes a first plurality of vias from the second surface through the substrate, the first plurality of vias being configured to couple to the electrical reference and to at least partially surround the first component. The device also includes a second plurality of vias from the second surface through the substrate, the second plurality of vias being configured to couple to the electrical reference and to at least partially surround the second component. The device also includes a conductive layer on the second surface of the substrate, the conductive layer is coupled to the first plurality of vias and the second plurality of vias to form a first electromagnetic shield and a second electromagnetic shield respectively for the first component and the second component.
Implementations may include one or more of the following features. The device where the first plurality of vias and the second plurality of vias may include a via-to-via pitch separation smaller than 1 mm to achieve at least −125 dB isolation between the light transmitter and the light detector to electromagnetic interference with characteristic frequencies up to 30 GHz. The metal layer may include a first section and a second section being separately grounded and respectively coupled with the first plurality of vias and the second plurality of vias. The conductive layer may include a first portion and a second portion respectively coupled with the first section and the second section to be associated with the first electromagnetic shield and the second electromagnetic shield respectively, the first electromagnetic shield being decoupled from the second electromagnetic shield. Embodiments of the subject technology are illustrated by examples shown below.
As shown in
The PIC 100 is based on a silicon substrate 101 with a frontside and a backside. The frontside may be referred to as first surface and the backside may be referred to second surface, the second surface being opposite to the first surface. The PIC 100 may include a first photonic subcircuit and a second photonic subcircuit co-packaged on the frontside of the silicon substrate. The first photonic subcircuit may include at least one light transmission component and the second photonic subcircuit may include at least one light detection component. Light transmission components, including light generation components like laser (and laser driver), light amplification components like optical amplifier, light modulation components like optical modulator, and optical transmitter, usually are large electromagnetic field emitters to cause high electromagnetic interference to neighboring devices. On the other hand, the light detection components including photodetectors (PDs) like photodiodes (PIN diodes or avalanche PDs), optical receivers (including signal processing), and optical sensors, usually generate low electromagnetic interference themselves but being highly sensitive to the electromagnetic interference from other circuits. In the example as shown in
Referring to
In general, an electrical reference, often referred to as a reference plane or reference net, is a stable point of known voltage against which other electrical potentials are measured. This reference is crucial in the design and analysis of electronic circuits and systems. In some embodiments, this reference net is a “ground” or “common” node in a circuit physically connecting part of an electrical system to the Earth, which serves as a universally available reference point. In some embodiments, “ground” does not refer to a physical connection to the Earth but rather to a point that is designated as the zero-voltage reference for the circuit. Optionally, an electrical reference net is a grounded layer of metal. A reference net or plane in a printed circuit board (PCB) design or in a substrate of a circuit die is a grid or a layer of conductive material (usually copper) that acts as a common return path for current and a reference voltage level. It can also provide a continuous, low-impedance path for the return of high-frequency signals, which can help reduce noise and electromagnetic interference (EMI).
The PIC 100 is stacked up on the EIC 200 by directly bonded the second group of electrical contacts on the third surface 3 via solders 160 to the first group of electrical contacts on the second surface 2. Thus, modulator 130 in PIC 100 would perform its signal modulation function based on driving signal delivered from Tx driver subcircuit 230 in EIC 200. Rx amplifier subcircuit 240 would also perform its amplification function to electrical signals output from photodiode 140. Here is just a simplified description for a single signal transmission/receiving (Tx-Rx) channel for the device. Optionally, there are multiple Tx-Rx channels of transmitters and receivers. Optionally, the modulator design employs a transmission line of a finite length at a certain characteristic impedance. Depending on the manufacturing process, this transmission line may be unshielded. Such unshielded transmission line often causes electric and magnetic fields which can permeate through the three-dimensional stack of PIC-over-EIC in all three directions. The lateral spreading of electromagnetic field in the X and
Y dimensions could possibly be terminated by those conducting vias on the reference net. In the Z direction the electromagnetic field induced by some active components including transmitter subcircuit, however, may propagate unhindered in the PIC bulk silicon substrate 101 or beyond to generate electrical crosstalk with other subcircuits in the PIC including receiver subcircuit that has sensitive circuitry like photodiode. For PIC with co-packaged subcircuits, not limited to just transmitter or receiver subcircuits, proper electrical shielding would be critical to suppress high frequency electrical coupling between the closely packaged subcircuits.
For general purpose, the term “integrated circuit (IC)” mentioned here in the specification (or maybe simplified as “circuit”) refers to a miniature electronic device that incorporates various electronic components, such as transistors, diodes, resistors, and capacitors, onto a single semiconductor substrate configured with a one or more functions. It refers typically to an electronic IC or EIC, also commonly known as a microchip or chip. A “photonic integrated circuit (PIC)” is a miniaturized electronic device that integrates specifically various photonic components and functions onto a single chip. Similar to EIC, photonic integrated circuits provide compact and highly integrated solutions for controlling and manipulating light signals. It typically incorporates a combination of active and passive optical components, including lasers, modulators, detectors, waveguides, splitters, couplers, filters, and other optical elements. Either EIC or PIC may include multiple subcircuits co-packaged in the same chip. A “subcircuit” refers to one unit device with a specific function configured within the “circuit”. For example, a “transmitter subcircuit” refers to a unit device of PIC that performs light transmission which includes functions like light signal generation (laser), signal modulation, power amplification, wavelength division, or others. A subcircuit of a PIC may be coupled with a subcircuit of an EIC, for example, a modulator in the transmitter subcircuit may need a driver subcircuit in the EIC to allow digital signals, i.e., data, to be properly transmitted via the light signals. An Rx amplifier subcircuit in the EIC may receive and process electrical signal delivered from a photodiode converting a light signal to the electrical signal in the PIC. As multiple subcircuits are co-packaged in one PIC chip, crosstalk between these subcircuits, especially for some subcircuits that generate high-frequency electric field to interfere sensitive detection circuitry in some other subcircuits.
For example, multiple vias 451, 452, 461, 462 are formed from the backside of the silicon substrate 101 to perpendicularly penetrate through the silicon substrate to reach the metal layer of the reference net. Before forming these through-silicon vias, the silicon substrate 101 can be thinned down to about the same thickness, e.g., 65 um, as the EIC 200. After the vias are formed through a series of masking, lithographing, etching, and cleaning processes, they can be filled with metal materials to be electrically conductive and be able to share the same potential with the reference net, e.g., being commonly grounded. In an embodiment, these vias are formed with selected locations such that a first plurality of vias, like via 451 and via 452, is configured to surround the first photonic subcircuit including at least the modulator 130 and a second plurality of vias, like via 461 and via 462, is configured to surround the second photonic subcircuit including at least the photodiode 140. In an embodiment, these vias are not necessarily physically next to each other to form a solid wall, instead, are formed with a certain via-to-via pitch distance. Depending on the types of photonics circuits and applications, the electrical electromagnetic interference between the different subcircuits may have different frequency of concerns. For example, the transmission line-based modulator may cause electromagnetic interference (EMI) to neighboring light detection circuitry mostly at frequency range from 13 GHz to 25 GHz. Based on fiber optic transceivers, the common bandwidths range from 5 GHz to 30 GHZ. These frequency ranges correspond to wavelengths greater than 10 mm. If the via pitch distance is set to as small as 1 mm, i.e., about 10% of the EMI wavelength, these vias can effectively block the EMI field spreading. In X-Y dimensions, the first plurality of vias (e.g., vias 451, vias 452) effectively forms a wall of shield surrounding the first photonic subcircuit and the second plurality of vias (e.g., vias 361, vias 462) also effectively forms a wall of shield surrounding the second photonic subcircuit.
Further referring to
Optionally, the conductive layer 410 can be separated to two sections, a first section is associated with the first electrical shielding cage only for shielding the first photonic subcircuit and a second section is associated with the second electrical shielding cage for shielding the second photonic subcircuit. In some embodiments, two metal plates can be added to couple with the two sections of the conductive layer 410. A first metal plate 421 is attached to the first section of the conductive layer, and a second metal plate 422, isolated from the first metal plate 421, can be attached to the second section of the conductive layer. This is also compatible with the optional setup of two separate reference nets as suggested in some embodiments. Then, the two electrical shielding cages can be independently grounded. The grounded metal plate 421 can effectively terminate the electromagnetic fields to prevent the EMI field spreading from the first subcircuit (e.g., the modulator with transmission line) into the neighboring second subcircuit (e.g., the photodiode). For example, it may be advantageous to have an “Rx GND” and a “Tx GND” reference net in the PIC as well as EIC. In some embodiments, the reference nets in the system (if it is set in the printed circuit board) would be connected together to have one common ground.
The receiver 140 also has 4 channels each including at least a photodiode, e.g., 141, 142, 143, and 144. The photodiode is very sensitive to the EMI caused by the other circuits nearby. Particularly, at the optical input terminals, denoted as RxIn0, RxIn1, RxIn2, and RxIn3. The optical input terminal of a receiver is typically designed to detect and amplify weak optical signals. EMI can introduce additional noise or interference, reducing the receiver's sensitivity and potentially degrading its ability to accurately detect and interpret the incoming signal. EMI can increase the noise floor of the receiver, decreasing the overall signal-to-noise ratio. This can impact the receiver's ability to distinguish the desired signal from unwanted noise, leading to a degradation in the quality and reliability of the received data. High levels of EMI can result in errors in the received data stream, increasing the bit error rate of the system. This can lead to data corruption, loss of synchronization, and decreased overall system performance. Therefore, it is important to have an electromagnetic shield to enclose at least the Rx input terminals to prevent the environmental electromagnetic field especially generated by neighboring subcircuits from interfering the performance of the receiver subcircuit.
Referring to
Additionally, in vertical direction (perpendicular to the reference net 120), a shielding structure can be formed, with the purpose of surrounding at least the transmitter 130 or the receiver 140. In an embodiment, the shielding structure is a plurality of conductive columns laid along the dashed line shown in
In some embodiments, an electromagnetic shielding cage for this silicon photonics device is provided by, 1) setting a reference net 120 under the photonics subcircuits to be electrically grounded; 2) forming a plurality of vias 450 and 460 (with locations indicated schematically by dashed lines in
Curve 501 corresponds to a model without shielding (at least in Z direction) for a silicon photonic device with 3D stacking of a photonic IC on an electronic IC (see
Curve 502 corresponds to a model with an electromagnetic shield based on conductive vias and backside metallization for a same kind of silicon photonics device (see
Curve 503 corresponds to a reference model without full shielding but just an RF absorber being placed on the backside of the silicon substrate of the photonic integrated circuit. The results suggest that the added RF absorber provides only a small improvement in crosstalk isolation. A 2D field mapping for this model (not shown) also indicates that there is still substantial field spreading from the Tx Output to Rx Input. This proves that the method and structure for shielding Tx-Rx crosstalk in photonic integrated circuit in this disclosure effectively suppresses high frequency electrical coupling between two photonic subcircuits like a transmitter and a receiver at a very fundamental level.
While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the subject technology which is defined by the appended claims.
