Patent Application
20140112062
In deep submicron technology nodes, increased process variation and device reliability issues place challenges in low power SRAM design. SRAMs occupy up to or more than 70% of the SoC area and therefore, SRAM area, power, performance and leakage are significant deciding factors in overall budgeting of SoC. With an ever increasing SRAM usage, and SRAM complexity, system level requirements are imposing increasing constraints on SRAM designs for improving key parameters like area, speed, leakage, dynamic power, etc. A unique feature of SRAMs, such as a 6 transistor SRAM, is an inherent trade-off between stability when holding data during a read or non-column selected write access and the ability of the cell to be written. This means that device dimensions and threshold voltage targets established for SRAM devices are compromise by design. The ability to read and write is characterized in terms of margins to assess the functional implications. It is difficult to design SRAM cells which are stable for both read and write without a large area overhead in SRAM cell size. Accordingly, an often used methodology is to make the cell stable for read by making pass-gate strength small and use a write-assist technique for write robustness. One other requirement on write ability of SRAMs is to write proper data in SRAM cells within the specified time.
An embodiment of the invention may therefore comprise a method of producing capacitive coupling in a memory architecture, the memory architecture comprising a plurality of bitcell rows and bitcell columns and at least one layer, the method comprising placing at least one pair of metal lines over the rows of bitcells in an upper metal layer of the memory architecture wherein the metal lines produces a negative boost to bitlines in the memory architecture.
An embodiment of the invention may further comprise a system of producing capacitive coupling in a memory architecture, said system comprising a MUX select signal, an input data signal, a BOOST signal, a selected bitline, a write common node and a boost capacitor, wherein a write passgate turns on in response to the MUX select and input data signal, the boost signal is asserted high to discharge the bitline and write common node, and when it is determined that the bitline and write common node have been discharged to a Vss level, the boost signal is asserted low to produce capacitive coupling on the selected bitline and write common node with the boost capacitor.
The design of SRAM cells has traditionally involved a compromise between the read and write functions of the memory array to maintain cell stability, read performance and write performance. In particular, the transistors which make up the cross-coupled latch must be weak enough to be overdriven during a write operation, while also strong enough to maintain their data value when driving a bit-line during a read operation. The access transistors that connect the cross-coupled inverters to the true and complement bit-lines affect both the stability and performance of the cell. It is understood that while the description of the invention may refer to SRAM type memories, the invention is not limited to SRAM. The techniques, methods and systems disclosed herein are equally applicable to other memory types, such as CAM and other memory architectures.
For a smaller number of rows in the SRAM, when bitline capacitance is much lesser than common node (WRCOM) capacitance and cross coupling capacitance between metal lines may be insufficient to provide a sufficient amount of boost capacitance, small sized MOS devices may be used. The MOS device can be sized as per the smaller number of rows to counter act common node (WRCOM) capacitance. This causes very less overhead area. As the number of rows increases, cross coupling capacitance and resultant boost capacitance increases. In an embodiment of the invention, MOS device size can be determined as per smaller number of rows (such as less than or equal to 32 rows) and metal lines, to provide cross coupling, are placed in redundant area so that it causes very little area overhead—approximately 1% to 3% based upon instance configuration.
In response to MUX select signal (Wsel0 and Wsel1) and input data (Din and DinB), one of the write pass-gates turn on.
The BOOST signal can be generated by use a variety of circuits. For example, the BOOST signal can be generated by WRCOM or bit-line discharge detection in another. Also, the BOOST signal could be generated by detection of discharge of a reference bit-line. Consistent with the invention, using a cross coupling capacitor as a boost capacitor is a way to generate control signals to generate the BOOST signal.
If there is not an X pitch remaining to route additional metal lines, the coupling between existing routed signals, which are not used during a write operation, can be used to provide coupling. For example, capacitive coupling between global read bit-line pair (GRDT and GRDC, as shown in
Shrinking technology is forcing reduction in metal line width which gives a benefit of reduced capacitance. At the same time, however, in order to maintain reasonable resistivity, its thickness needs to be also increased. As a result, the impact of cross coupling capacitance (capacitance within the same metal layers) is increasing with shrinking feature sizes. In an embodiment of the invention, it is proposed to utilize this cross coupling capacitance so that the effectiveness of the proposed circuit will increase with smaller feature sizes. Further, the structure and methods of the invention disclosed herein can be helped with the use of MOSFETS, MISFETS, FINFETS and other field effect, and similar, devices.
It is understood that the methods and systems provide herein may be used to provide negative or positive coupling to other global lines in the memory architecture. These boosts may enhance memory performance such as access, setup time, etc.
The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.
