The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
Referring now to the Figures for the purpose of illustration, it is to be understood that standard components or features that are within the purview of an artisan of ordinary skill and do not contribute to the understanding of the various exemplary embodiments are omitted from the Figures to enhance clarity.
The point where data from the persistent memory model 28 is being used to verify the correctness of read response data from the processor 14 or persistent data is referenced by processor 14 or 10 bus functional models. The use of global visibility with a persistent memory model 28 takes advantage of the fact that the bus coherent operation now has the exclusive ownership of the coherent address with the acknowledgement of the whole system. Accordingly, the data in the persistent memory model 28 can be updated for writes and compared against the data response for reads. Additionally, the use of global visibility with a persistent memory model 28 ensures that no matter where the actual data resides for a given coherent address, there will be only one valid value for the data at that address.
In exemplary embodiments, the unit monitor checker 26 tracks the coherent memory operation from the external bus interface through the internal hardware logic to the point where the operation becomes globally visible to the whole system. At this point, the processor store data can be copied into the persistent memory model 28. For processor reads, the content of the persistent memory model 28 can be saved to compare it against the read data response later.
In exemplary embodiments the persistent memory model 28 operates in conjunction with the global visibility point for different types of coherent memory operations including persistent data update operations and persistent data reference operations.
In one exemplary embodiment, specific sequences should be followed for persistent data update operations. For example, during a processor read operation the persistent memory address should already be preloaded before the read. In another example, during a processor internal store the persistent data is updated with the internal store data. During a processor write-back the persistent data should already be updated before the write-back. Additionally, during an IO DMA load the persistent memory address should already be preloaded before the load. Further, during an IO DMA store the persistent data will be updated with the DMA store data when the store becomes globally visible. The global visibility point indicates the cache line ownership for the store address was obtained by hardware.
In another exemplary embodiment, specific sequences should be followed for persistent data reference operations. For example, during a processor read command the persistent data will be compared against the actual read response data. In another example, during a processor write-back command the persistent data will be compared against the actual write-back data. During an IO DMA load command the persistent data will be saved when the load becomes globally visible. The global visibility point indicates the cache line ownership for the load address was obtained by hardware. This persistent data snapshot will be used later for comparison against the actual DMA Read Response Data on the IO interface. Further, during an IO DMA store command the persistent data will be compared against the actual Store Data on the processor interface.
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While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.