Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole

Abstract

A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 illustrates a flowchart of a preferred method of enhancing the yield of semiconductor integrated circuit devices according to an embodiment of the invention;

FIG. 2 illustrates a diagram of an example of a test pattern representing experimental values;

FIG. 3 illustrates a diagram of step S20 of FIG. 1;

FIGS. 4A, 4B and 5 illustrate diagrams of step S40 of FIG. 1;

FIG. 6 illustrates a diagram of step S50 of FIG. 1;

FIG. 7 illustrates a flowchart of a preferred method of enhancing the yield of semiconductor integrated circuit devices according to another embodiment of the invention;

FIG. 8 illustrates a block diagram of a system for enhancing the yield of semiconductor integrated circuit devices according to a preferred embodiment of the invention; and

FIG. 9 illustrates a block diagram of a system for enhancing the yield of semiconductor integrated circuit devices according to another preferred embodiment of the invention.

Claims

1. A method of enhancing yield of semiconductor integrated circuit devices, comprising: determining a plurality of experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole;forming a plurality of test patterns representing each of the experimental values on a wafer;calculating experimental value-based systematic fault rates from the plurality of test patterns;converting the experimental value-based systematic fault rates of the hole into experimental value-based systematic fault rates per unit hole length using a length of the sides of the hole of each of the test patterns;calculating the length of the side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values in a desired layout; andcalculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the each of experimental values in the desired layout.

2. The method as claimed in claim 1, wherein the experimental values are taken at increments of a predetermined interval from a minimum design rule value for the distances between the sides of the hole and the opposing sides of the shape surrounding the hole.

3. The method as claimed in claim 2, wherein the predetermined interval is a design grid or a multiple of the design grid.

4. The method as claimed in claim 1, wherein the calculating the experimental value-based systematic fault rates comprises: counting a number of test patterns in which at least one fault occurs among the plurality of test patterns on the wafer corresponding to each of experiment values;measuring the experimental value-based fault rates of the hole; andclassifying the measured experimental value-based fault rates into experimental value-based random fault rates and experimental value-based systematic fault rates.

5. The method as claimed in claim 4, wherein the experimental value-based fault rates converge to a specific value as the experimental value increases, and the experimental value-based random fault rates are a convergence value and the experimental value-based systematic fault rate is a difference between the experimental value-based fault rate and the experimental value-based random fault rate.

6. The method as claimed in claim 1, wherein, in the each of test patterns, the distances between four sides of the hole and four sides of the shape surrounding the hole are uniform, and the converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates per unit hole length comprises dividing each of the experimental value-based systematic fault rates by a sum of lengths of the four sides of the hole, thereby performing conversion into the experimental value-based systematic fault rate per unit hole length.

7. The method as claimed in claim 1, wherein the calculating the length of the side of the hole in the layout of interest for each of the experimental values is performed by calculating the length of the side of the hole for each non-redundant hole in the desired layout for each of the experimental values.

8. The method as claimed in claim 1, wherein: at least one of the sides of the hole includes a plurality of sub-sides, and distances between sub-sides of the hole and the opposite sides of the shape are different; andthe calculating the length of the side of the hole, for which the distance between the side of the hole and the opposite side of the shape corresponds to each of the experimental values, comprises calculating a length of the sub-side of the hole, for which the distance between the sub-side of the hole and an opposing side of the shape corresponds to each of the experimental values.

9. The method as claimed in claim 1, wherein the calculating the systematic fault rate of the hole is performed using the following equation:

10. The method as claimed in claim 1, further comprising calculating a systematic yield of the hole using the systematic fault rate of the hole; and correcting the distances between the sides of the hole and the opposing sides of the shape in the desired layout in consideration of the systematic yield.

11. A method of enhancing yield of semiconductor integrated circuit devices, comprising: determining a plurality of experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole;forming a plurality of test patterns representing each of the experimental values on a wafer;counting a number of test patterns in which a fault occurs;measuring experimental value-based fault rates of the hole;classifying the measured experimental value-based fault rates into experimental value-based random fault rates and experimental value-based systematic fault rates;calculating a random fault rate and a systematic fault rate of the hole for a desired layout using the experimental value-based random fault rates and the experimental value-based systematic fault rates; andcalculating a total fault rate of the hole in the desired layout using the random fault rate and systematic fault rate of the hole.

12. The method as claimed in claim 11, wherein the experimental value-based fault rates converge to a specific value as the experimental value increases, the experimental value-based random fault rates are a convergence value, and the experimental value-based systematic fault rate is a difference between the experimental value-based fault rate and the experimental value-based random fault rate.

13. The method as claimed in claim 11, wherein the calculating the random fault rate of the hole is performed by multiplying a number of non-redundant holes in the desired layout by the experimental value-based random fault rate.

14. The method as claimed in claim 11, wherein the calculating the systematic fault rate of the hole comprises: converting the experimental value-based systematic fault rates of the hole into experimental value-based systematic fault rates per unit hole length using a length of the sides of the hole of each of the test patterns;calculating a length of the side of the hole, for which the distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values in the layout of interest; andcalculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the side of the hole calculated for the each of experimental values in the desired layout,wherein, in the each of test patterns, the distances between four sides of the hole and four sides of the shape surrounding the hole are uniform.

15. The method as claimed in claim 14, wherein the converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates per unit hole length comprises: dividing each of the experimental value-based systematic fault rates by a sum of lengths of four sides of the hole, thereby performing conversion into the experimental value-based systematic fault rates per unit hole length.

16. The method as claimed in claim 14, wherein the calculating the length of the side of the hole in the layout of interest for each of the experimental values is performed by calculating the length of the side of the hole or each non-redundant hole in the desired layout for each of the experimental values.

17. The method as claimed in claim 14, wherein: at least one of the sides of the hole includes a plurality of sub-sides, and the distances between sub-sides of the hole and the opposing sides of the shape are different; andthe calculating the length of the side of the hole, for which the distance between the side of the hole and the opposite side of the line corresponds to each of the experimental values, comprises calculating a length of the sub-side of the hole for which the distance between the sub-side of the hole and an opposing side of the shape corresponds to each of the experimental values.

18. A system for enhancing yield of semiconductor integrated circuit devices, the system comprising: a first storage unit storing a plurality of experimental values determined for distances between sides of a hole and opposing sides of a shape surrounding the hole;a second storage unit storing experimental value-based systematic fault rates of the hole calculated from a plurality of test patterns after the plurality of test patterns representing each of the experimental values have been formed on a wafer;a conversion unit converting the experimental value-based systematic fault rates into experimental value-based systematic fault rate per unit hole length using a length of sides of the hole of each of the test patterns;a first calculation unit calculating a length of a side of the hole, for which the distance between the side of a hole and the opposing side of the shape corresponds to an experimental value in a desired layout; anda second calculation unit receiving the experimental value-based systematic fault rates per unit hole length from the conversion unit and the length of the side of the hole calculated for each of experimental values in the desired layout from the first calculation unit and calculating the systematic fault rate of the hole.

19. A mask manufactured using the system of enhancing the layouts of semiconductor integrated circuit devices as claimed in claim 18.

20. A semiconductor integrated circuit device manufactured using the mask as claimed in claim 19.