BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a sequence of frames generated using a method for frame insertion that implements motion estimation and motion compensation, according to the prior art.
FIG. 2 illustrates a sequence of frames generated using a method for frame insertion that implements black frames in a digital display system, according to the prior art.
FIG. 3 illustrates an exemplary method for frame insertion in a digital display system, according to one embodiment of the present invention.
FIG. 4 illustrates a method for implementing frame insertion in a digital display system, according to one embodiment of the present invention.
FIG. 5 illustrates a system for frame insertion in a digital display system, according to another embodiment of the present invention.
FIG. 6 illustrates an exemplary signal timing diagram for the system of FIG. 5.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The present invention will now be described in detail with reference to the drawings, which are provided as illustrative examples of the invention so as to enable those skilled in the art to practice the invention. Notably, the implementation of certain elements of the present invention may be accomplished using software, hardware, firmware or any combination thereof, as would be apparent to those of ordinary skill in the art, and the figures and examples below are not meant to limit the scope of the present invention. Moreover, where certain elements of the present invention can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present invention will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the invention. Preferred embodiments of the present invention are illustrated in the Figures, like numerals being used to refer to like and corresponding parts of various drawings.
In one embodiment of the present invention, a method for frame insertion is used to generate frames in a digital display system, such as an LCD monitor. The method reduces motion blur with a limited sacrifice to the overall brightness of the digital display. The method involves generating “modified” frames, which are each based on a previous input frame multiplied by a reduced luminance factor, and interspersing the modified frames with the input frames to create a sequence of output frames.
FIG. 3 illustrates a sequence of output frames generated using the method according to this embodiment. In one embodiment, the method may be designed to operate on an LCD monitor that implements a double scan approach. However, the method may also be implemented on other types of monitors using other types of scanning methods. In a double scan LCD monitor, the frequency of input video (e.g., N, for example, 50/60 Hz video) is doubled (e.g., converted to N*2, for example, 100/120 Hz) on the LCD monitor. As shown in FIG. 3, the input frames are illustrated as A, B, C, D . . . . Due to the double-scan nature of the monitor, the output frames generated will include twice as many frames, which will be output at twice the frequency of the input sequence. According to this embodiment, the output sequence is A, a*A, B, a*B, C, a*C, D, a*D . . . . The frames A, B, C and D represent the digitized input frames. Interspersed between the digitized input frames are modified frames a*A, a*B, a*C and a*D, which represent the inserted frames. The inserted frames are substantially similar to the digitized input frames, but have a reduced luminance. For example, each modified frame may be equal to the preceding digitized input frame multiplied by a reduce luminance factor “a”. The reduced luminance factor can be a constant value or an adaptive variable representing some percentage less than or equal to 100%. In one embodiment, the reduced luminance factor may vary be between 0 and 1. The reduced luminance factor may also be calculated as a function of the average picture level or “APL” of the corresponding frame A, B, C, D. In this embodiment, the method determines an APL for each frame A, B, C, and D using conventional methods known to those of ordinary skill in the art. The method then calculates the reduced luminance factor “a” as a function of this APL for each frame. For example, the factor “a” for frame a*A would be equal to f(APLFrame A), the factor “a” for frame a*B be would be equal to f(APLFrame B), and so forth. In this manner, frames with higher APLs may have corresponding modified frames with higher luminance levels. In one embodiment, the factor “a” is proportional to the APL. The foregoing method provides an output sequence of frames that substantially reduces or eliminates the motion blur problem without significantly affecting the overall brightness of the display.
Because the foregoing method does not require complex algorithms for interpolation using MEMC, it can be implemented relatively easily without excessive dedicated processing resources. Furthermore, because the method does not insert black frames, the sacrifice to the overall brightness of the display is significantly reduced.
FIG. 4 illustrates a process of implementing frame insertion in a digital display system, according an embodiment of the present invention. While this embodiment is primarily described in relation to a method 100, it should be appreciated that each of the portions or blocks illustrated in FIG. 1 may represent logic blocks that may be implemented using conventional hardware, software, or firmware and/or any combination of hardware, software and firmware.
Method 100 may be implemented on a digital display system, such as an LCD display, which receives a sequence of input frames from a video source at a first frequency and outputs digitized frames at a second frequency, which may be double the first frequency. In one example, the input frequency is N (for example, 50/60 Hz) and output frequency is N*2 (for example, 100/120 Hz). In step 102, an input frame is received and digitized. The digitized frame may be stored in a frame buffer or memory. In step 104, the digitized input frame is read from the frame buffer or memory. In step 106, the method displays the digitized input frame on the LCD display. In step 108, the method generates a modified frame for insertion. The modified frame may be substantially similar to the digitized input frame, but having a reduced luminance. In one embodiment, the modified frame is equal to the digitized input frame multiplied by a reduced luminance factor “a” (e.g., the luminance value for each pixel of the frame may be multiplied by the reduced factor “a”). The reduced luminance factor “a” may be a constant value or may be variable (e.g., adaptive). For example, the reduced luminance factor “a” may be calculated as a function of the APL of the preceding input frame as previously described. In step 110, the method displays the modified frame. And in step 112, the method proceeds to the next input frame and repeats. In this manner, the method 100 generates a sequence of output frames that comprise the digitized input frames interspersed with modified frames of reduced luminance. One skilled in the art will appreciate that the each of the steps 102 through 112 do not have to occur in the sequence illustrated in FIG. 4. Certain steps may be occurring simultaneously and/or in a different order. For example, step 108 may occur before and/or during step 106. Additionally, those skilled in the art will appreciate that the digitized input frames and/or modified frames may undergo conventional filtering and processing before display.
FIG. 5 illustrates one embodiment of a system 200 that may be used to implement the present invention in a digital television system. In one embodiment, portions of system 200 may reside within or comprise a display controller for a LCD monitor. The circuitry shown in FIG. 5 may be formed from conventional hardware elements (e.g., circuits), software elements, firmware elements and/or any combination thereof. In one embodiment, system 200 includes a frame buffer 202, a vertical sync signal adjustment module or circuit 204, a double scan read-out module or circuit 206, an average pixel level (“APL”) detection module or circuit 208, a processing module or circuit 210, a divider circuit 212, a multiplier circuit 214, and an output multiplexer 216. The frame buffer 202 is coupled to the double scan read-out module 206, which selectively reads frames out of the buffer 202. The double scan read-out module 206 is coupled to and receives an adjusted vertical sync signal (“VSYNC*2”) from vertical sync adjustment module 204. The output of vertical sync adjustment module 204 is also coupled to divider circuit 212, which is coupled to and provides the switching signal (“SWITCH”) for multiplexer 216. The output of module 206 is coupled to APL detection module 208, to multiplier circuit 214 and to a first input of multiplexer 216. The APL detection module 208 is coupled to the processing module 210, which is coupled to multiplier circuit 214. The output of multiplier circuit 214 is coupled to a second input of multiplexer 216. The output of multiplexer 216 may be communicated to a LCD monitor for display. It should be appreciated that the system 200 shown in FIG. 5 may also include additional or different circuits or modules. Only those elements useful for an understanding of the invention have been depicted and described. Additionally, those skilled in the art will appreciate that the digitized input frames and/or modified frames may be filtered and processed by conventional filtering and processing circuitry before display.
The following discussion describes the operation of the system 200 and its components. In operation, the system 200 receives an input sequence of frames from a video source at a first frequency (e.g., N, for example, 50/60 Hz) and generates a sequence of output frames at a second frequency, which may be double the first frequency. The output frames include digitized versions of the input frames interspersed with modified frames, which are substantially equivalent to the input frames multiplied by a reduced luminance factor “a”. Frame buffer 202 stores the digitized input frames in the sequence (e.g., frames A, B, C, D, etc., shown in FIG. 3). Vertical sync adjustment module 204 receives the vertical sync signal from the input sequence (i.e., VSYNC), which is set to a first frequency. In one embodiment, the first frequency may be N (for example, 50-60 Hz). In other embodiments, any suitable input frequency may be used. The vertical sync adjustment module 204, which may be a portion of the display controller, doubles the frequency of the vertical sync signal to generate an output signal “VSYNC*2” (for example, at 100-120 Hz). This output signal is communicated to the double scan read-out module 206 and to the divider circuit 212. The divider circuit 212 generates a switching signal (SWITCH) that switches value (from 0 to 1) upon detecting a rising edge of an input pulse. FIG. 6 illustrates exemplary wave forms for the input VSYNC signal, VSYNC*2 and SWITCH. At each pulse of VSYNC*2, read-out module 206 reads a frame from the frame buffer 202. Because the frame buffer 202 is receiving frames at the first frequency and the module 206 is reading frames out of the frame buffer at twice the speed, the module reads each frame in the frame buffer 202 twice (e.g., A, A, B, B, C, C, D, D, etc.). Each digitized frame is output to a first input of the multiplexer 216 and to the multiplication circuit 214. The APL detection block 208 uses conventional APL detection methods to determine the average pixel level of each frame, which represents the average brightness or luminance of each frame. The processing block 210 uses the APL value to calculate a reduced luminance factor “a”. In one embodiment, the reduced luminance factor is proportional to the APL. The reduced luminance factor “a” is output to the multiplier block 214. The multiplier block 214 multiplies the luminance factor “a” with the current frame to generate a modified frame of reduced luminance (e.g., a*A, b*B, c*C, a*D, etc.), which is communicated to the second input of the multiplexer 216. The SWITCH signal causes multiplexer 216 to selectively switch its output between the first input to the second input, thereby selectively alternating between a digitized input frame and a corresponding modified frame. The resulting output would be similar to that shown in FIG. 3, namely, A, a*A, B, a*B, C, a*C, D, a*D, etc.
From the foregoing, it should be apparent that the embodiments disclosed provide improved methods and systems for frame insertion in a digital display system, such as an LCD monitor. The methods and systems reduce motion blur without requiring complex MEMC processing and with reduced sacrifice to the overall brightness of the monitor.
While the foregoing has been with reference to particular embodiments of the invention, it will be appreciated by those skilled in the art that changes in these embodiments may be made without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims.
Patent Application
20070296655
