Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

Information

  • Patent Grant
  • 9396161
  • Patent Number
    9,396,161
  • Date Filed
    Monday, May 18, 2015
    9 years ago
  • Date Issued
    Tuesday, July 19, 2016
    8 years ago
Abstract
An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.
Description
BACKGROUND OF THE INVENTION

The present invention relates, in general, to integrated circuits and, more particularly, to adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.


The advances made in the design and development of integrated circuits (“ICs”) have generally produced ICs of several different types or categories having different properties and functions, such as the class of universal Turing machines (including microprocessors and digital signal processors (“DSPs”), application specific integrated circuits (“ASICs”), and field programmable gate arrays (“FPGAs”)). Each of these different types of ICs, and their corresponding design methodologies, have distinct advantages and disadvantages.


Microprocessors and DSPs, for example, typically provide a flexible, software programmable solution for the implementation of a wide variety of tasks. As various technology standards evolve, microprocessors and DSPs may be reprogrammed, to varying degrees, to perform various new or altered functions or operations. Various tasks or algorithms, however, must be partitioned and constrained to fit the physical limitations of the processor, such as bus widths and hardware availability. In addition, as processors are designed for the execution of instructions, large areas of the IC are allocated to instruction processing, with the result that the processors are comparatively inefficient in the performance of actual algorithmic operations, with only a few percent of these operations performed during any given clock cycle. Microprocessors and DSPs, moreover, have a comparatively limited activity factor, such as having only approximately five percent of their transistors engaged in algorithmic operations at any given time, with most of the transistors allocated to instruction processing. As a consequence, for the performance of any given algorithmic operation, processors consume significantly more IC (or silicon) area and consume significantly more power compared to other types of ICs, such as ASICs.


While having comparative advantages in power consumption and size, ASICs provide a fixed, rigid or “hard-wired” implementation of transistors (or logic gates) for the performance of a highly specific task or a group of highly specific tasks. ASICs typically perform these tasks quite effectively, with a comparatively high activity factor, such as with twenty-five to thirty percent of the transistors engaged in switching at any given time. Once etched, however, an ASIC is not readily changeable, with any modification being time-consuming and expensive, effectively requiring new masks and new fabrication. As a further result, ASIC design virtually always has a degree of obsolescence, with a design cycle lagging behind the evolving standards for product implementations. For example, an ASIC designed to implement GSM or CDMA standards for mobile communication becomes relatively obsolete with the advent of a new standard, such as 3G.


FPGAs have evolved to provide some design and programming flexibility, allowing a degree of post-fabrication modification. FPGAs typically consist of small, identical sections or “islands” of programmable logic (logic gates) surrounded by many levels of programmable interconnect, and may include memory elements. FPGAs are homogeneous, with the IC comprised of repeating arrays of identical groups of logic gates, memory and programmable interconnect. A particular function may be implemented by configuring (or reconfiguring) the interconnect to connect the various logic gates in particular sequences and arrangements. The most significant advantage of FPGAs are their post-fabrication reconfigurability, allowing a degree of flexibility in the implementation of changing or evolving specifications or standards. The reconfiguring process for an FPGA is comparatively slow, however, and is typically unsuitable for most real-time, immediate applications.


While this post-fabrication flexibility of FPGAs provides a significant advantage, FPGAs have corresponding and inherent disadvantages. Compared to ASICs, FPGAs are very expensive and very inefficient for implementation of particular functions, and are often subject to a “combinatorial explosion” problem. More particularly, for FPGA implementation, an algorithmic operation comparatively may require orders of magnitude more IC area, time and power, particularly when the particular algorithmic operation is a poor fit to the pre-existing, homogeneous islands of logic gates of the FPGA material. In addition, the programmable interconnect, which should be sufficiently rich and available to provide reconfiguration flexibility, has a correspondingly high capacitance, resulting in comparatively slow operation and high power consumption. For example, compared to an ASIC, an FPGA implementation of a relatively simple function, such as a multiplier, consumes significant IC area and vast amounts of power, while providing significantly poorer performance by several orders of magnitude. In addition, there is a chaotic element to FPGA routing, rendering FPGAs subject to unpredictable routing delays and wasted logic resources, typically with approximately one-half or more of the theoretically available gates remaining unusable due to limitations in routing resources and routing algorithms.


Various prior art attempts to meld or combine these various processor, ASIC and FPGA architectures have had utility for certain limited applications, but have not proven to be successful or useful for low power, high efficiency, and real-time applications. Typically, these prior art attempts have simply provided, on a single chip, an area of known FPGA material (consisting of a repeating array of identical logic gates with interconnect) adjacent to either a processor or an ASIC, with limited interoperability, as an aid to either processor or ASIC functionality. For example, Trimberger U.S. Pat. No. 5,737,631, entitled “Reprogrammable Instruction Set Accelerator”, issued Apr. 7, 1998, is designed to provide instruction acceleration for a general purpose processor, and merely discloses a host CPU made up of such a basic microprocessor combined in parallel with known FPGA material (with an FPGA configuration store, which together form the reprogrammable instruction set accelerator). This reprogrammable instruction set accelerator, while allowing for some post-fabrication reconfiguration flexibility and processor acceleration, is nonetheless subject to the various disadvantages of traditional processors and traditional FPGA material, such as high power consumption and high capacitance, with comparatively low speed, low efficiency and low activity factors.


Tavana et al. U.S. Pat. No. 6,094,065, entitled “Integrated Circuit with Field Programmable and Application Specific Logic Areas”, issued Jul. 25, 2000, is designed to allow a degree of post-fabrication modification of an ASIC, such as for correction of design or other layout flaws, and discloses use of a field programmable gate array in a parallel combination with a mask-defined application specific logic area (i.e., ASIC material). Once again, known FPGA material, consisting of a repeating array of identical logic gates within a rich programmable interconnect, is merely placed adjacent to ASIC material within the same silicon chip. While potentially providing post-fabrication means for “bug fixes” and other error correction, the prior art IC is nonetheless subject to the various disadvantages of traditional ASICs and traditional FPGA material, such as highly limited reprogrammability of an ASIC, combined with high power consumption, comparatively low speed, low efficiency and low activity factors of FPGAs.


As a consequence, it would be desirable to have a new form or type of integrated circuitry which effectively and efficiently combines and maximizes the various advantages of processors, ASICs and FPGAs, while minimizing potential disadvantages.


In addition, due to the disadvantages of many conventional hardware components, such as processors, ASICs and FPGAs, as described above, hardware components used to implement many functions and/or algorithms in a traditional hardware-based system are permanently dedicated to such functions and/or algorithms. In other words, when a particular function and/or algorithm is not utilized, the associated hardware components remain idle. It would be beneficial and more efficient if the idle hardware components can be used to carry out other functions and/or algorithms within the system.


For example, in a traditional cellular phone, during power-up, a large portion of the circuitry within the cellular phone sits idle waiting for the receiver circuitry to perform system acquisition. The amount of acquisition time is directly proportional to the amount of hardware dedicated to the system acquisition task. Traditionally, the dedicated hardware is optimized based on cost trade-off and system acquisition time and is often much closer sized to the needs of the receiver during traffic mode than during system acquisition. As a result, when acquiring a signal in an unknown environment, e.g., the operating channel is different from the last channel used at power-down, the receiver may spend a large amount of time to acquire the new channel. The time necessary to acquire a signal in an unknown environment may range from seconds to minutes. However, since system acquisition is only performed at power-up, long acquisition times in cases where a new system is encountered is considered an acceptable trade-off. Nevertheless, shorter system acquisition times would still be desirable. Hence, it would be desirable to have a new form or type of integrated circuitry which allows hardware resources to be managed or allocated more efficiently so as to enhance the performance of a system.


Moreover, since hardware components in a traditional hardware-based system are permanently dedicated to their associated functions and/or algorithms, adding and implementing new functions and/or algorithms would require adding hardware components. Due to physical limitations, adding hardware components to a system may not be possible. Consequently, it would also be desirable to have a new form or type of integrated circuitry which allows additional functions and/or algorithms to be added and implemented in a system without incurring significant hardware costs.


SUMMARY OF THE INVENTION

The present invention provides a new form or type of integrated circuitry which effectively and efficiently combines and maximizes the various advantages of processors, ASICs and FPGAs, while minimizing potential disadvantages. In accordance with the present invention, such a new form or type of integrated circuit, referred to as an adaptive computing engine (ACE), is disclosed which provides the programming flexibility of a processor, the post-fabrication flexibility of FPGAs, and the high speed and high utilization factors of an ASIC. The ACE integrated circuitry of the present invention is readily reconfigurable, in real-time, is capable of having corresponding, multiple modes of operation, and further minimizes power consumption while increasing performance, with particular suitability for low power applications, such as for use in hand-held and other battery-powered devices.


The ACE architecture of the present invention, for adaptive or reconfigurable computing, includes a plurality of heterogeneous computational elements coupled to an interconnection network, rather than the homogeneous units of FPGAs. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.


As illustrated and discussed in greater detail below, the ACE architecture of the present invention provides a single IC, which may be configured and reconfigured in real-time, using these fixed and application specific computation elements, to perform a wide variety of tasks. For example, utilizing differing configurations over time of the same set of heterogeneous computational elements, the ACE architecture may implement functions such as finite impulse response filtering, fast Fourier transformation, discrete cosine transformation, and with other types of computational elements, may implement many other high level processing functions for advanced communications and computing.


Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to accompanying drawings, like reference numbers indicate identical or functionally similar elements.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a block diagram illustrating an exemplary embodiment of the present invention;



FIG. 2 is a schematic diagram illustrating an exemplary data flow graph in accordance with the present invention;



FIG. 3 is a block diagram illustrating a reconfigurable matrix, a plurality of computation units, and a plurality of computational elements, in accordance with the present invention;



FIG. 4 is a block diagram illustrating, in greater detail, a computational unit of a reconfigurable matrix in accordance with the present invention;



FIGS. 5A through 5E are block diagrams illustrating, in detail, exemplary fixed and specific computational elements, forming computational units, in accordance with the present invention;



FIGS. 6A through 6D are block diagrams illustrating, in detail, an exemplary multi-function adaptive computational unit having a plurality of different, fixed computational elements, in accordance with the present invention;



FIG. 7 is a block diagram illustrating, in detail, an exemplary adaptive logic processor computational unit having a plurality of fixed computational elements, in accordance with the present invention;



FIG. 8 is a block diagram illustrating, in greater detail, an exemplary core cell of an adaptive logic processor computational unit with a fixed computational element, in accordance with the present invention;



FIG. 9 is a block diagram illustrating, in greater detail, an exemplary fixed computational element of a core cell of an adaptive logic processor computational unit, in accordance with the present invention; and



FIGS. 10-13 are block diagrams respectively illustrating re-allocation and re-configuration of hardware resources in accordance with the present invention.





DETAILED DESCRIPTION OF THE INVENTION

As indicated above, it would be desirable to have a new form or type of integrated circuitry which effectively and efficiently combines and maximizes the various advantages of processors, ASICs and FPGAs, while minimizing potential disadvantages. In accordance with the present invention, such a new form or type of integrated circuit, referred to as an adaptive computing engine (ACE), is disclosed which provides the programming flexibility of a processor, the post-fabrication flexibility of FPGAs, and the high speed and high utilization factors of an ASIC. The ACE integrated circuitry of the present invention is readily reconfigurable, in real-time, is capable of having corresponding, multiple modes of operation, and further minimizes power consumption while increasing performance, with particular suitability for low power applications.



FIG. 1 is a block diagram illustrating an exemplary apparatus 100 embodiment in accordance with the present invention. The apparatus 100, referred to herein as an adaptive computing engine (“ACE”) 100, is preferably embodied as an integrated circuit, or as a portion of an integrated circuit having other, additional components. In the exemplary embodiment, and as discussed in greater detail below, the ACE 100 includes one or more reconfigurable matrices (or nodes) 150, such as matrices 150A through 150N as illustrated, and a matrix interconnection network 110. Also in the exemplary embodiment, and as discussed in detail below, one or more of the matrices 150, such as matrices 150A and 150B, are configured for functionality as a controller 120, while other matrices, such as matrices 150C and 150D, are configured for functionality as a memory 140. The various matrices 150 and matrix interconnection network 110 may also be implemented together as fractal subunits, which may be scaled from a few nodes to thousands of nodes.


The ACE 100 does not utilize traditional (and typically separate) data, DMA, random access, configuration and instruction busses for signaling and other transmission between and among the reconfigurable matrices 150, the controller 120, and the memory 140, or for other input/output (“I/O”) functionality. Rather, data, control and configuration information are transmitted between and among these matrix 150 elements, utilizing the matrix interconnection network 110, which may be configured and reconfigured, in real-time, to provide any given connection between and among the reconfigurable matrices 150, including those matrices 150 configured as the controller 120 and the memory 140, as discussed in greater detail below.


The matrices 150 configured to function as memory 140 may be implemented in any desired or exemplary way, utilizing computational elements (discussed below) of fixed memory elements, and may be included within the ACE 100 or incorporated within another IC or portion of an IC. In the exemplary embodiment, the memory 140 is included within the ACE 100, and preferably is comprised of computational elements which are low power consumption random access memory (RAM), but also may be comprised of computational elements of any other form of memory, such as flash, DRAM, SRAM, MRAM, ROM, EPROM or E2PROM. In the exemplary embodiment, the memory 140 preferably includes direct memory access (DMA) engines, not separately illustrated.


The controller 120 is preferably implemented, using matrices 150A and 150B configured as adaptive finite state machines, as a reduced instruction set (“RISC”) processor, controller or other device or IC capable of performing the two types of functionality discussed below. (Alternatively, these functions may be implemented utilizing a conventional RISC or other processor.) The first control functionality, referred to as “kernal” control, is illustrated as kernal controller (“KARC”) of matrix 150A, and the second control functionality, referred to as “matrix” control, is illustrated as matrix controller (“MARC”) of matrix 150B. The kernal and matrix control functions of the controller 120 are explained in greater detail below, with reference to the configurability and reconfigurability of the various matrices 150, and with reference to the exemplary form of combined data, configuration and control information referred to herein as a “silverware” module.


The matrix interconnection network 110 of FIG. 1, and its subset interconnection networks separately illustrated in FIGS. 3 and 4 (Boolean interconnection network 210, data interconnection network 240, and interconnect 220), collectively and generally referred to herein as “interconnect”, “interconnection(s)” or “interconnection network(s)”, may be implemented generally as known in the art, such as utilizing FPGA interconnection networks or switching fabrics, albeit in a considerably more varied fashion. In the exemplary embodiment, the various interconnection networks are implemented as described, for example, in U.S. Pat. Nos. 5,218,240, 5,336,950, 5,245,227, and 5,144,166, and also as discussed below and as illustrated with reference to FIGS. 7, 8 and 9. These various interconnection networks provide selectable (or switchable) connections between and among the controller 120, the memory 140, the various matrices 150, and the computational units 200 and computational elements 250 discussed below, providing the physical basis for the configuration and reconfiguration referred to herein, in response to and under the control of configuration signaling generally referred to herein as “configuration information”. In addition, the various interconnection networks (110, 210, 240 and 220) provide selectable or switchable data, input, output, control and configuration paths, between and among the controller 120, the memory 140, the various matrices 150, and the computational units 200 and computational elements 250, in lieu of any form of traditional or separate input/output busses, data busses, DMA, RAM, configuration and instruction busses.


It should be pointed out, however, that while any given switching or selecting operation of or within the various interconnection networks (110, 210, 240 and 220) may be implemented as known in the art, the design and layout of the various interconnection networks (110, 210, 240 and 220), in accordance with the present invention, are new and novel, as discussed in greater detail below. For example, varying levels of interconnection are provided to correspond to the varying levels of the matrices 150, the computational units 200, and the computational elements 250, discussed below. At the matrix 150 level, in comparison with the prior art FPGA interconnect, the matrix interconnection network 110 is considerably more limited and less “rich”, with lesser connection capability in a given area, to reduce capacitance and increase speed of operation. Within a particular matrix 150 or computational unit 200, however, the interconnection network (210, 220 and 240) may be considerably more dense and rich, to provide greater adaptation and reconfiguration capability within a narrow or close locality of reference.


The various matrices or nodes 150 are reconfigurable and heterogeneous, namely, in general, and depending upon the desired configuration: reconfigurable matrix 150A is generally different from reconfigurable matrices 150B through 150N; reconfigurable matrix 150B is generally different from reconfigurable matrices 150A and 150C through 150N; reconfigurable matrix 150C is generally different from reconfigurable matrices 150A, 150B and 150D through 150N, and so on. The various reconfigurable matrices 150 each generally contain a different or varied mix of adaptive and reconfigurable computational (or computation) units (200); the computational units 200, in turn, generally contain a different or varied mix of fixed, application specific computational elements (250), discussed in greater detail below with reference to FIGS. 3 and 4, which may be adaptively connected, configured and reconfigured in various ways to perform varied functions, through the various interconnection networks. In addition to varied internal configurations and reconfigurations, the various matrices 150 may be connected, configured and reconfigured at a higher level, with respect to each of the other matrices 150, through the matrix interconnection network 110, also as discussed in greater detail below.


Several different, insightful and novel concepts are incorporated within the ACE 100 architecture of the present invention, and provide a useful explanatory basis for the real-time operation of the ACE 100 and its inherent advantages.


The first novel concepts of the present invention concern the adaptive and reconfigurable use of application specific, dedicated or fixed hardware units (computational elements 250), and the selection of particular functions for acceleration, to be included within these application specific, dedicated or fixed hardware units (computational elements 250) within the computational units 200 (FIG. 3) of the matrices 150, such as pluralities of multipliers, complex multipliers, and adders, each of which are designed for optimal execution of corresponding multiplication, complex multiplication, and addition functions. Given that the ACE 100 is to be optimized, in the exemplary embodiment, for low power consumption, the functions for acceleration are selected based upon power consumption. For example, for a given application such as mobile communication, corresponding C (C+ or C++) or other code may be analyzed for power consumption. Such empirical analysis may reveal, for example, that a small portion of such code, such as 10%, actually consumes 90% of the operating power when executed. In accordance with the present invention, on the basis of such power utilization, this small portion of code is selected for acceleration within certain types of the reconfigurable matrices 150, with the remaining code, for example, adapted to run within matrices 150 configured as controller 120. Additional code may also be selected for acceleration, resulting in an optimization of power consumption by the ACE 100, up to any potential trade-off resulting from design or operational complexity. In addition, as discussed with respect to FIG. 3, other functionality, such as control code, may be accelerated within matrices 150 when configured as finite state machines.


Next, algorithms or other functions selected for acceleration are converted into a form referred to as a “data flow graph” (“DFG”). A schematic diagram of an exemplary data flow graph, in accordance with the present invention, is illustrated in FIG. 2. As illustrated in FIG. 2, an algorithm or function useful for CDMA voice coding (QCELP (Qualcomm code excited linear prediction) is implemented utilizing four multipliers 190 followed by four adders 195. Through the varying levels of interconnect, the algorithms of this data flow graph are then implemented, at any given time, through the configuration and reconfiguration of fixed computational elements (250), namely, implemented within hardware which has been optimized and configured for efficiency, i.e., a “machine” is configured in real-time which is optimized to perform the particular algorithm. Continuing with the exemplary DFG or FIG. 2, four fixed or dedicated multipliers, as computational elements 250, and four fixed or dedicated adders, also as different computational elements 250, are configured in real-time through the interconnect to perform the functions or algorithms of the particular DFG.


The third and perhaps most significant concept of the present invention, and a marked departure from the concepts and precepts of the prior art, is the concept of reconfigurable “heterogeneity” utilized to implement the various selected algorithms mentioned above. As indicated above, prior art reconfigurability has relied exclusively on homogeneous FPGAs, in which identical blocks of logic gates are repeated as an array within a rich, programmable interconnect, with the interconnect subsequently configured to provide connections between and among the identical gates to implement a particular function, albeit inefficiently and often with routing and combinatorial problems. In stark contrast, in accordance with the present invention, within computation units 200, different computational elements (250) are implemented directly as correspondingly different fixed (or dedicated) application specific hardware, such as dedicated multipliers, complex multipliers, and adders. Utilizing interconnect (210 and 220), these differing, heterogeneous computational elements (250) may then be adaptively configured, in real-time, to perform the selected algorithm, such as the performance of discrete cosine transformations often utilized in mobile communications. For the data flow graph example of FIG. 2, four multipliers and four adders will be configured, i.e., connected in real-time, to perform the particular algorithm. As a consequence, in accordance with the present invention, different (“heterogeneous”) computational elements (250) are configured and reconfigured, at any given time, to optimally perform a given algorithm or other function. In addition, for repetitive functions, a given instantiation or configuration of computational elements may also remain in place over time, i.e., unchanged, throughout the course of such repetitive calculations.


The temporal nature of the ACE 100 architecture should also be noted. At any given instant of time, utilizing different levels of interconnect (110, 210, 240 and 220), a particular configuration may exist within the ACE 100 which has been optimized to perform a given function or implement a particular algorithm. At another instant in time, the configuration may be changed, to interconnect other computational elements (250) or connect the same computational elements 250 differently, for the performance of another function or algorithm. Two important features arise from this temporal reconfigurability. First, as algorithms may change over time to, for example, implement a new technology standard, the ACE 100 may co-evolve and be reconfigured to implement the new algorithm. For a simplified example, a fifth multiplier and a fifth adder may be incorporated into the DFG of FIG. 2 to execute a correspondingly new algorithm, with additional interconnect also potentially utilized to implement any additional bussing functionality. Second, because computational elements are interconnected at one instant in time, as an instantiation of a given algorithm, and then reconfigured at another instant in time for performance of another, different algorithm, gate (or transistor) utilization is maximized, providing significantly better performance than the most efficient ASICs relative to their activity factors.


This temporal reconfigurability of computational elements 250, for the performance of various different algorithms, also illustrates a conceptual distinction utilized herein between configuration and reconfiguration, on the one hand, and programming or reprogrammability, on the other hand. Typical programmability utilizes a pre-existing group or set of functions, which may be called in various orders, over time, to implement a particular algorithm. In contrast, configurability and reconfigurability, as used herein, includes the additional capability of adding or creating new functions which were previously unavailable or non-existent.


Next, the present invention also utilizes a tight coupling (or interdigitation) of data and configuration (or other control) information, within one, effectively continuous stream of information. This coupling or commingling of data and configuration information, referred to as a “silverware” module, is the subject of a separate, related patent application. For purposes of the present invention, however, it is sufficient to note that this coupling of data and configuration information into one information (or bit) stream helps to enable real-time reconfigurability of the ACE 100, without a need for the (often unused) multiple, overlaying networks of hardware interconnections of the prior art. For example, as an analogy, a particular, first configuration of computational elements at a particular, first period of time, as the hardware to execute a corresponding algorithm during or after that first period of time, may be viewed or conceptualized as a hardware analog of “calling” a subroutine in software which may perform the same algorithm. As a consequence, once the configuration of the computational elements has occurred (i.e., is in place), as directed by the configuration information, the data for use in the algorithm is immediately available as part of the silverware module. The same computational elements may then be reconfigured for a second period of time, as directed by second configuration information, for execution of a second, different algorithm, also utilizing immediately available data. The immediacy of the data, for use in the configured computational elements, provides a one or two clock cycle hardware analog to the multiple and separate software steps of determining a memory address and fetching stored data from the addressed registers. This has the further result of additional efficiency, as the configured computational elements may execute, in comparatively few clock cycles, an algorithm which may require orders of magnitude more clock cycles for execution if called as a subroutine in a conventional microprocessor or DSP.


This use of silverware modules, as a commingling of data and configuration information, in conjunction with the real-time reconfigurability of a plurality of heterogeneous and fixed computational elements 250 to form adaptive, different and heterogenous computation units 200 and matrices 150, enables the ACE 100 architecture to have multiple and different modes of operation. For example, when included within a hand-held device, given a corresponding silverware module, the ACE 100 may have various and different operating modes as a cellular or other mobile telephone, a music player, a pager, a personal digital assistant, and other new or existing functionalities. In addition, these operating modes may change based upon the physical location of the device; for example, when configured as a CDMA mobile telephone for use in the United States, the ACE 100 may be reconfigured as a GSM mobile telephone for use in Europe.


Referring again to FIG. 1, the functions of the controller 120 (preferably matrix (KARC) 150A and matrix (MARC) 150B, configured as finite state machines) may be explained with reference to a silverware module, namely, the tight coupling of data and configuration information within a single stream of information, with reference to multiple potential modes of operation, with reference to the reconfigurable matrices 150, and with reference to the reconfigurable computation units 200 and the computational elements 150 illustrated in FIG. 3. As indicated above, through a silverware module, the ACE 100 may be configured or reconfigured to perform a new or additional function, such as an upgrade to a new technology standard or the addition of an entirely new function, such as the addition of a music function to a mobile communication device. Such a silverware module may be stored in the matrices 150 of memory 140, or may be input from an external (wired or wireless) source through, for example, matrix interconnection network 110. In the exemplary embodiment, one of the plurality of matrices 150 is configured to decrypt such a module and verify its validity, for security purposes. Next, prior to any configuration or reconfiguration of existing ACE 100 resources, the controller 120, through the matrix (KARC) 150A, checks and verifies that the configuration or reconfiguration may occur without adversely affecting any pre-existing functionality, such as whether the addition of music functionality would adversely affect pre-existing mobile communications functionality. In the exemplary embodiment, the system requirements for such configuration or reconfiguration are included within the silverware module, for use by the matrix (KARC) 150A in performing this evaluative function. If the configuration or reconfiguration may occur without such adverse affects, the silverware module is allowed to load into the matrices 150 of memory 140, with the matrix (KARC) 150A setting up the DMA engines within the matrices 150C and 150D of the memory 140 (or other stand-alone DMA engines of a conventional memory). If the configuration or reconfiguration would or may have such adverse affects, the matrix (KARC) 150A does not allow the new module to be incorporated within the ACE 100.


Continuing to refer to FIG. 1, the matrix (MARC) 150B manages the scheduling of matrix 150 resources and the timing of any corresponding data, to synchronize any configuration or reconfiguration of the various computational elements 250 and computation units 200 with any corresponding input data and output data. In the exemplary embodiment, timing information is also included within a silverware module, to allow the matrix (MARC) 150B through the various interconnection networks to direct a reconfiguration of the various matrices 150 in time, and preferably just in time, for the reconfiguration to occur before corresponding data has appeared at any inputs of the various reconfigured computation units 200. In addition, the matrix (MARC) 150B may also perform any residual processing which has not been accelerated within any of the various matrices 150. As a consequence, the matrix (MARC) 150B may be viewed as a control unit which “calls” the configurations and reconfigurations of the matrices 150, computation units 200 and computational elements 250, in real-time, in synchronization with any corresponding data to be utilized by these various reconfigurable hardware units, and which performs any residual or other control processing. Other matrices 150 may also include this control functionality, with any given matrix 150 capable of calling and controlling a configuration and reconfiguration of other matrices 150.



FIG. 3 is a block diagram illustrating, in greater detail, a reconfigurable matrix 150 with a plurality of computation units 200 (illustrated as computation units 200A through 200N), and a plurality of computational elements 250 (illustrated as computational elements 250A through 250Z), and provides additional illustration of the exemplary types of computational elements 250 and a useful summary of the present invention. As illustrated in FIG. 3, any matrix 150 generally includes a matrix controller 230, a plurality of computation (or computational) units 200, and as logical or conceptual subsets or portions of the matrix interconnect network 110, a data interconnect network 240 and a Boolean interconnect network 210. As mentioned above, in the exemplary embodiment, at increasing “depths” within the ACE 100 architecture, the interconnect networks become increasingly rich, for greater levels of adaptability and reconfiguration. The Boolean interconnect network 210, also as mentioned above, provides the reconfiguration and data interconnection capability between and among the various computation units 200, and is preferably small (i.e., only a few bits wide), while the data interconnect network 240 provides the reconfiguration and data interconnection capability for data input and output between and among the various computation units 200, and is preferably comparatively large (i.e., many bits wide). It should be noted, however, that while conceptually divided into reconfiguration and data capabilities, any given physical portion of the matrix interconnection network 110, at any given time, may be operating as either the Boolean interconnect network 210, the data interconnect network 240, the lowest level interconnect 220 (between and among the various computational elements 250), or other input, output, or connection functionality.


Continuing to refer to FIG. 3, included within a computation unit 200 are a plurality of computational elements 250, illustrated as computational elements 250A through 250Z (individually and collectively referred to as computational elements 250), and additional interconnect 220. The interconnect 220 provides the reconfigurable interconnection capability and input/output paths between and among the various computational elements 250. As indicated above, each of the various computational elements 250 consist of dedicated, application specific hardware designed to perform a given task or range of tasks, resulting in a plurality of different, fixed computational elements 250. Utilizing the interconnect 220, the fixed computational elements 250 may be reconfigurably connected together into adaptive and varied computational units 200, which also may be further reconfigured and interconnected, to execute an algorithm or other function, at any given time, such as the quadruple multiplications and additions of the DFG of FIG. 2, utilizing the interconnect 220, the Boolean network 210, and the matrix interconnection network 110.


In the exemplary embodiment, the various computational elements 250 are designed and grouped together, into the various adaptive and reconfigurable computation units 200 (as illustrated, for example, in FIGS. 5A through 9). In addition to computational elements 250 which are designed to execute a particular algorithm or function, such as multiplication or addition, other types of computational elements 250 are also utilized in the exemplary embodiment. As illustrated in FIG. 3, computational elements 250A and 250B implement memory, to provide local memory elements for any given calculation or processing function (compared to the more “remote” memory 140). In addition, computational elements 2501, 250J, 250K and 250L are configured to implement finite state machines (using, for example, the computational elements illustrated in FIGS. 7, 8 and 9), to provide local processing capability (compared to the more “remote” matrix (MARC) 150B), especially suitable for complicated control processing.


With the various types of different computational elements 250 which may be available, depending upon the desired functionality of the ACE 100, the computation units 200 may be loosely categorized. A first category of computation units 200 includes computational elements 250 performing linear operations, such as multiplication, addition, finite impulse response filtering, and so on (as illustrated below, for example, with reference to FIGS. 5A through 5E and FIG. 6). A second category of computation units 200 includes computational elements 250 performing non-linear operations, such as discrete cosine transformation, trigonometric calculations, and complex multiplications. A third type of computation unit 200 implements a finite state machine, such as computation unit 200C as illustrated in FIG. 3 and as illustrated in greater detail below with respect to FIGS. 7 through 9), particularly useful for complicated control sequences, dynamic scheduling, and input/output management, while a fourth type may implement memory and memory management, such as computation unit 200A as illustrated in FIG. 3. Lastly, a fifth type of computation unit 200 may be included to perform bit-level manipulation, such as for encryption, decryption, channel coding, Viterbi decoding, and packet and protocol processing (such as Internet Protocol processing).


In the exemplary embodiment, in addition to control from other matrices or nodes 150, a matrix controller 230 may also be included within any given matrix 150, also to provide greater locality of reference and control of any reconfiguration processes and any corresponding data manipulations. For example, once a reconfiguration of computational elements 250 has occurred within any given computation unit 200, the matrix controller 230 may direct that that particular instantiation (or configuration) remain intact for a certain period of time to, for example, continue repetitive data processing for a given application.



FIG. 4 is a block diagram illustrating, in greater detail, an exemplary or representative computation unit 200 of a reconfigurable matrix 150 in accordance with the present invention. As illustrated in FIG. 4, a computation unit 200 typically includes a plurality of diverse, heterogeneous and fixed computational elements 250, such as a plurality of memory computational elements 250A and 250B, and forming a computational unit (“CU”) core 260, a plurality of algorithmic or finite state machine computational elements 250C through 250K. As discussed above, each computational element 250, of the plurality of diverse computational elements 250, is a fixed or dedicated, application specific circuit, designed and having a corresponding logic gate layout to perform a specific function or algorithm, such as addition or multiplication. In addition, the various memory computational elements 250A and 250B may be implemented with various bit depths, such as RAM (having significant depth), or as a register, having a depth of 1 or 2 bits.


Forming the conceptual data and Boolean interconnect networks 240 and 210, respectively, the exemplary computation unit 200 also includes a plurality of input multiplexers 280, a plurality of input lines (or wires) 281, and for the output of the CU core 260 (illustrated as line or wire 270), a plurality of output demultiplexers 285 and 290, and a plurality of output lines (or wires) 291. Through the input multiplexers 280, an appropriate input line 281 may be selected for input use in data transformation and in the configuration and interconnection processes, and through the output demultiplexers 285 and 290, an output or multiple outputs may be placed on a selected output line 291, also for use in additional data transformation and in the configuration and interconnection processes.


In the exemplary embodiment, the selection of various input and output lines 281 and 291, and the creation of various connections through the interconnect (210, 220 and 240), is under control of control bits 265 from the computational unit controller 255, as discussed below. Based upon these control bits 265, any of the various input enables 251, input selects 252, output selects 253, MUX selects 254, DEMUX enables 256, DEMUX selects 257, and DEMUX output selects 258, may be activated or deactivated.


The exemplary computation unit 200 includes a computation unit controller 255 which provides control, through control bits 265, over what each computational element 250, interconnect (210, 220 and 240), and other elements (above) does with every clock cycle. Not separately illustrated, through the interconnect (210, 220 and 240), the various control bits 265 are distributed, as may be needed, to the various portions of the computation unit 200, such as the various input enables 251, input selects 252, output selects 253, MUX selects 254, DEMUX enables 256, DEMUX selects 257, and DEMUX output selects 258. The CU controller 295 also includes one or more lines 295 for reception of control (or configuration) information and transmission of status information.


As mentioned above, the interconnect may include a conceptual division into a data interconnect network 240 and a Boolean interconnect network 210, of varying bit widths, as mentioned above. In general, the (wider) data interconnection network 240 is utilized for creating configurable and reconfigurable connections, for corresponding routing of data and configuration information. The (narrower) Boolean interconnect network 210, while also utilized for creating configurable and reconfigurable connections, is utilized for control of logic (or Boolean) decisions of the various data flow graphs, generating decision nodes in such DFGs, and may also be used for data routing within such DFGs.



FIGS. 5A through 5E are block diagrams illustrating, in detail, exemplary fixed and specific computational elements, forming computational units, in accordance with the present invention. As will be apparent from review of these FIGS., many of the same fixed computational elements are utilized, with varying configurations, for the performance of different algorithms.



FIG. 5A is a block diagram illustrating a four-point asymmetric finite impulse response (FIR) filter computational unit 300. As illustrated, this exemplary computational unit 300 includes a particular, first configuration of a plurality of fixed computational elements, including coefficient memory 305, data memory 310, registers 315, 320 and 325, multiplier 330, adder 335, and accumulator registers 340, 345, 350 and 355, with multiplexers (MUXes) 360 and 365 forming a portion of the interconnection network (210, 220 and 240).



FIG. 5B is a block diagram illustrating a two-point symmetric finite impulse response (FIR) filter computational unit 370. As illustrated, this exemplary computational unit 370 includes a second configuration of a plurality of fixed computational elements, including coefficient memory 305, data memory 310, registers 315, 320 and 325, multiplier 330, adder 335, second adder 375, and accumulator registers 340 and 345, also with multiplexers (MUXes) 360 and 365 forming a portion of the interconnection network (210, 220 and 240).



FIG. 5C is a block diagram illustrating a subunit for a fast Fourier transform (FFT) computational unit 400. As illustrated, this exemplary computational unit 400 includes a third configuration of a plurality of fixed computational elements, including coefficient memory 305, data memory 310, registers 315, 320, 325 and 385, multiplier 330, adder 335, and adder/subtractor 380, with multiplexers (MUXes) 360, 365, 390, 395 and 405 forming a portion of the interconnection network (210, 220 and 240).



FIG. 5D is a block diagram illustrating a complex finite impulse response (FIR) filter computational unit 440. As illustrated, this exemplary computational unit 440 includes a fourth configuration of a plurality of fixed computational elements, including memory 410, registers 315 and 320, multiplier 330, adder/subtractor 380, and real and imaginary accumulator registers 415 and 420, also with multiplexers (MUXes) 360 and 365 forming a portion of the interconnection network (210, 220 and 240).



FIG. 5E is a block diagram illustrating a biquad infinite impulse response (IIR) filter computational unit 450, with a corresponding data flow graph 460. As illustrated, this exemplary computational unit 450 includes a fifth configuration of a plurality of fixed computational elements, including coefficient memory 305, input memory 490, registers 470, 475, 480 and 485, multiplier 330, and adder 335, with multiplexers (MUXes) 360, 365, 390 and 395 forming a portion of the interconnection network (210, 220 and 240).



FIGS. 6A-6D are a block diagram illustrating, in detail, an exemplary multi-function adaptive computational unit 500 having a plurality of different, fixed computational elements, in accordance with the present invention. When configured accordingly, the adaptive computation unit 500 performs each of the various functions previously illustrated with reference to FIGS. 5A through 5E, plus other functions such as discrete cosine transformation. As illustrated, this multi-function adaptive computational unit 500 includes capability for a plurality of configurations of a plurality of fixed computational elements, including input memory 520, data memory 525, registers 530 (illustrated as registers 530A through 530Q), multipliers 540 (illustrated as multipliers 540A through 540D), adder 545, first arithmetic logic unit (ALU) 550 (illustrated as ALU_1s 550A through 550D), second arithmetic logic unit (ALU) 555 (illustrated as ALU_2s 555A through 555D), and pipeline (length l) register 560, with inputs 505, lines 515, outputs 570, and multiplexers (MUXes or MXes) 510 (illustrates as MUXes and MXes 510A through 510KK) forming an interconnection network (210, 220 and 240). The two different ALUs 550 and 555 are preferably utilized, for example, for parallel addition and subtraction operations, particularly useful for radix 2 operations in discrete cosine transformation.



FIG. 7 is a block diagram illustrating, in detail, an exemplary adaptive logic processor (ALP) computational unit 600 having a plurality of fixed computational elements, in accordance with the present invention. The ALP 600 is highly adaptable, and is preferably utilized for input/output configuration, finite state machine implementation, general field programmability, and bit manipulation. The fixed computational element of ALP 600 is a portion (650) of each of the plurality of adaptive core cells (CCs) 610 (FIG. 8), as separately illustrated in FIG. 9. An interconnection network (210, 220 and 240) is formed from various combinations and permutations of the pluralities of vertical inputs (VIs) 615, vertical repeaters (VRs) 620, vertical outputs (VOs) 625, horizontal repeaters (HRs) 630, horizontal terminators (HTs) 635, and horizontal controllers (HCs) 640.



FIG. 8 is a block diagram illustrating, in greater detail, an exemplary core cell 610 of an adaptive logic processor computational unit 600 with a fixed computational element 650, in accordance with the present invention. The fixed computational element is a 3 input-2 output function generator 550, separately illustrated in FIG. 9. The exemplary core cell 610 also includes control logic 655, control inputs 665, control outputs 670 (providing output interconnect), output 675, and inputs (with interconnect muxes) 660 (providing input interconnect).



FIG. 9 is a block diagram illustrating, in greater detail, an exemplary fixed computational element 650 of a core cell 610 of an adaptive logic processor computational unit 600, in accordance with the present invention. The fixed computational element 650 is comprised of a fixed layout of pluralities of exclusive NOR (XNOR) gates 680, NOR gates 685, NAND gates 690, and exclusive OR (XOR) gates 695, with three inputs 720 and two outputs 710. Configuration and interconnection is provided through MUX 705 and interconnect inputs 730.


As may be apparent from the discussion above, this use of a plurality of fixed, heterogeneous computational elements (250), which may be configured and reconfigured to form heterogeneous computation units (200), which further may be configured and reconfigured to form heterogeneous matrices 150, through the varying levels of interconnect (110, 210, 240 and 220), creates an entirely new class or category of integrated circuit, which may be referred to as an adaptive computing architecture. It should be noted that the adaptive computing architecture of the present invention cannot be adequately characterized, from a conceptual or from a nomenclature point of view, within the rubric or categories of FPGAs, ASICs or processors. For example, the non-FPGA character of the adaptive computing architecture is immediately apparent because the adaptive computing architecture does not comprise either an array of identical logical units, or more simply, a repeating array of any kind. Also for example, the non-ASIC character of the adaptive computing architecture is immediately apparent because the adaptive computing architecture is not application specific, but provides multiple modes of functionality and is reconfigurable in real-time. Continuing with the example, the non-processor character of the adaptive computing architecture is immediately apparent because the adaptive computing architecture becomes configured, to directly operate upon data, rather than focusing upon executing instructions with data manipulation occurring as a byproduct.


Based on the disclosure provided herein, it should be clear to a person of ordinary skill in the art that the present invention offers a number of advantages when used in implementing a hardware-based system. For example, using the adaptive computing architecture as described above, hardware resources within a system can be utilized or allocated more efficiently and intelligently. For instance, when a specific function is not needed at a particular point in time, the associated hardware resources, including the matrices 150 and their constituent computation units 200 and computational elements 250, used to implement that specific function can be re-allocated and re-configured to implement one or more other functions which can benefit from the additional hardware resources.


The additional hardware resources can be utilized in a number of ways. For example, additional functional units which are used to carry out another function can be added by re-allocating and re-configuring some or all of the additional hardware resources to increase the parallel processing power thereby allowing faster execution of such function.


Consider a cdma2000 or W-CDMA cellular phone for example. At power-up, a single searcher is typically used to perform system acquisition and the majority of the communication or radio functions of the cellular phone are idle. The implementation of a single searcher is commonly known in the art. Now consider a cellular phone implemented with the adaptive computing architecture described herein. Hardware resources, which would have been needed if the idle communication or radio functions were active, can be re-allocated to perform the system acquisition function at a time when system acquisition is needed, such as when the cellular phone is initially powered up. That is, additional instances of the searcher can be implemented to provide more parallel processing power thereby allowing the system acquisition function to be performed faster. The number of additional instances of the searcher to be implemented depends on the amount of hardware resources which are available and/or other factors such as design choice and system constraints and requirements etc.


Referring to FIG. 10, for example, at the time the cellular phone is initially powered up, three instances of the searcher 1002, 1004 and 1006 are implemented to speed up the system acquisition process. Subsequently, when the system acquisition process is completed, some or all of the hardware resources which were used to implement the system acquisition function may be de-allocated and then re-allocated and re-configured to implement one or more communication functions 1008 which are to become active shortly.


In another example, some or all of the additional hardware resources can be re-allocated and re-configured to provide a modified or alternative implementation of an existing function. Again, consider the cellular phone implemented with the adaptive computing architecture described herein. The additional hardware resources can be used to implement a modified or alternative searcher which can perform the system acquisition function in a faster manner. Referring to FIG. 11, for example, hardware resources for the searcher 1102 and the communication function 1104 are re-allocated and re-configured to implement the searcher 1106. In this case, instead of using the additional hardware resources to implement multiple instances of the searcher (which is a viable alternative), the additional hardware resources are used to implement one instance of a modified or alternative searcher. If sufficient hardware resources are available, the modified or alternative searcher may provide better performance than a number of smaller searchers operating in parallel. Likewise, the choice as to whether to use the additional hardware resources to implement one instance of a modified or alternative searcher depends on the amount of hardware resources which are available and/or other factors such as design choice and system constraints and requirements etc.


In yet another example, some or all of the additional hardware resources can be re-allocated and re-configured to provide an additional function which is implemented subject to availability of the hardware resources. Such additional function may be an independent function that is to be added to the system or an optional or supplemental function that works in cooperation with another existing function. Similarly, the additional hardware resources may be re-allocated and re-configured as either multiple functional units or a single functional unit to provide the additional function. Referring to FIG. 12, for example, hardware resources for the searcher 1204 are de-allocated and re-allocated and re-configured to implement the additional communication function 1208. The choice as to how to use the additional hardware resources to implement the additional function depends on the amount of hardware resources which are available and/or other factors such as design choice and system constraints and requirements etc.


In a further example, some or all of the hardware resources being used to implement an existing function may be de-allocated and then re-allocated and re-configured to implement an additional function and the existing function in a different manner. Again, using the cellular phone implemented with the adaptive computing architecture described herein as an example. Referring to FIG. 13, for example, hardware resources may be initially allocated to implement one version of the searcher 1302 which has a higher level of performance. When the need to implement another function 1308 arises, some of the previously allocated hardware resources may be de-allocated and then re-allocated and re-configured to implement this other function 1308, and the remaining hardware resources previously allocated to implement one version of the searcher 1302 may be re-allocated and re-configured to implement another version of the searcher 1306 which has a lower level of performance. While a cellular phone having a searcher is used herein as an example, it should be clear to a person of ordinary skill in the art that the present invention can be similarly applied to other types of communication devices having a system acquisition functionality including, for example, communication devices which utilize Bluetooth and 802.11 technology.


Other advantages of the present invention may be further apparent to those of skill in the art. For mobile communications, for example, hardware acceleration for one or two algorithmic elements has typically been confined to infrastructure base stations, handling many (typically 64 or more) channels. Such an acceleration may be cost justified because increased performance and power savings per channel, performed across multiple channels, results in significant performance and power savings. Such multiple channel performance and power savings are not realizable, using prior art hardware acceleration, in a single operative channel mobile terminal (or mobile unit). In contrast, however, through use of the present invention, cost justification is readily available, given increased performance and power savings, because the same IC area may be configured and reconfigured to accelerate multiple algorithmic tasks, effectively generating or bringing into existence a new hardware accelerator for each next algorithmic element.


Yet additional advantages of the present invention may be further apparent to those of skill in the art. The ACE 100 architecture of the present invention effectively and efficiently combines and maximizes the various advantages of processors, ASICs and FPGAs, while minimizing potential disadvantages. The ACE 100 includes the programming flexibility of a processor, the post-fabrication flexibility of FPGAs, and the high speed and high utilization factors of an ASIC. The ACE 100 is readily reconfigurable, in real-time, and is capable of having corresponding, multiple modes of operation. In addition, through the selection of particular functions for reconfigurable acceleration, the ACE 100 minimizes power consumption and is suitable for low power applications, such as for use in hand-held and other battery-powered devices.


It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims. All publications, patents, and patent applications cited herein are hereby incorporated by reference for all purposes in their entirety.

Claims
  • 1. An adaptive computing integrated circuit configurable to perform a plurality of functions, comprising: a plurality of heterogeneous computational elements; andan interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network operative to configure the plurality of heterogeneous computational elements by changing interconnections between the plurality of heterogeneous computational elements;wherein a first group of heterogeneous computational elements is configurable by changing the interconnections of the interconnection network to form a first functional unit to implement a first function, the first function capable of being performed in parallel by multiple functional units;wherein a second group of heterogeneous computational elements is configurable by changing interconnections of the interconnection network to form a second functional unit to implement a second function; andwherein if the second function is not currently used, one or more of the second group of heterogeneous computational elements are reconfigurable by changing the interconnections of the interconnection network to implement the first function in parallel with the first group of heterogeneous computational elements.
  • 2. The adaptive computing integrated circuit of claim 1, wherein the first functional unit forms a first version of a functional unit to implement the first function and wherein the one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form one or more additional instances of a second version of the functional unit to implement the first function.
  • 3. The adaptive computing integrated circuit of claim 2, wherein one or more of the first group of heterogeneous computational elements or one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form a third version of a functional unit to implement the first function.
  • 4. The adaptive integrated circuit of claim 2, wherein the second group of computational elements is reconfigured to the second version of the functional unit to perform the first function based on parameters including energy use, speed of performing the first function, or hardware availability.
  • 5. The adaptive integrated circuit of claim 2, further comprising reallocating the first group of computational elements to perform a third function by changing the interconnections of the interconnection network after the second group of computational elements is reconfigured to the second version of the functional unit.
  • 6. The adaptive computing integrated circuit of claim 1 wherein if the second function is not currently used, one or more of the first or second group of heterogeneous computational elements are reconfigurable by the interconnection network to implement a third function.
  • 7. The adaptive computing integrated circuit of claim 1, wherein a third group of computational elements are configured to implement a third function, wherein the third group of computational elements are reconfigured as one of the multiple functional units to perform the first function if the third function is not used.
  • 8. The adaptive integrated circuit of claim 1, wherein the first and second functions are part of a sequential operation and wherein the one or more of the second group of heterogeneous computational elements is reconfigured to perform the second function after the first function is performed.
  • 9. An adaptive computing integrated circuit configurable to perform a plurality of functions, comprising: a plurality of heterogeneous computational elements; andan interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network operative to configure the plurality of heterogeneous computational elements by changing interconnections between the plurality of heterogeneous computational elements;wherein a first group of heterogeneous computational elements is configurable by changing the interconnections of the interconnection network to form a first functional unit to implement a first function;wherein a second group of heterogeneous computational elements is configurable by changing interconnections of the interconnection network to form a second functional unit to implement a second function; andwherein enhanced performance of the first function is executed by reconfiguring one or more of the second group of heterogeneous computational elements via changing the interconnections of the interconnection network to perform the first function.
  • 10. The adaptive computing integrated circuit of claim 9, wherein the enhanced performance is executed by one or more of the second group of heterogeneous computational elements being reconfigured to form another functional unit to implement the first function.
  • 11. The adaptive computing integrated circuit of claim 9, wherein one or more of the second group of computational elements are reconfigured to form a different version of a functional unit to perform the first function.
  • 12. The adaptive computing integrated circuit of claim 9 wherein if the second function is not currently used, the one or more of the second group of heterogeneous computational elements are reconfigurable by the interconnection network to implement a third function.
  • 13. The adaptive computing integrated circuit of claim 12, wherein a third group of the heterogeneous computational elements is allocated to implement the third function.
  • 14. The adaptive computing integrated circuit of claim 9, wherein the enhanced version of the functional unit is formed based on a parameter including decreased energy use, increase speed of performing the function or hardware availability.
  • 15. The adaptive integrated circuit of claim 9, wherein the first and second functions are part of a sequential operation and wherein the one or more of the second group of heterogeneous computational elements is reconfigured to perform the second function after the first function is performed according to the configuration information.
  • 16. A method for allocating hardware computational elements within an adaptive computing integrated circuit, comprising: in response to first configuration information, allocating a first group of computational elements of the plurality of heterogeneous computational elements to form a first functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements, the first function capable of being performed in parallel by multiple function units;allocating a second group of computational elements of the plurality of heterogeneous computational elements to form a second functional unit to implement a second function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements; andreallocating at least some of the second group of heterogeneous computational elements allocated to the second functional unit to implement the first function in parallel with the first group of heterogeneous computational elements by changing the interconnections of the interconnection network.
  • 17. The method of claim 16, wherein the second group of computational elements is reconfigured to the second version of the functional unit to perform the first function based on parameters including energy use, speed of performing the first function, or hardware availability.
  • 18. The method of claim 16, wherein the first functional unit forms a first version of a functional unit to implement the first function and wherein the one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form one or more additional instances of a second version of the functional unit to implement the first function.
  • 19. The method of claim 16, wherein one or more of the first group of heterogeneous computational elements or one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form a third version of a functional unit to implement the first function.
  • 20. The method of claim 16, further comprising reallocating a third group of computational elements configured to implement a third function to be reconfigured as one of the multiple functional units to perform the first function if the third function is not used.
CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 14/082,691, filed Nov. 18, 2013, which is a continuation of application Ser. No. 12/785,868, filed May 24, 2010, now U.S. Pat. No. 8,589,660 which is a continuation of application Ser. No. 10/015,530 filed on Dec. 12, 2001 entitled “METHOD AND SYSTEM FOR MANAGING HARDWARE RESOURCES TO IMPLEMENT SYSTEM FUNCTIONS USING AN ADAPTIVE COMPUTING ARCHITECTURE”, the contents of which are all incorporated herein by reference.

US Referenced Citations (516)
Number Name Date Kind
3409175 Byrne Nov 1968 A
3666143 Weston May 1972 A
3938639 Birrell Feb 1976 A
3949903 Benasutti et al. Apr 1976 A
3960298 Birrell Jun 1976 A
3967062 Dobias Jun 1976 A
3991911 Shannon et al. Nov 1976 A
3995441 McMillin Dec 1976 A
4076145 Zygiel Feb 1978 A
4143793 McMillin et al. Mar 1979 A
4172669 Edelbach Oct 1979 A
4174872 Fessler Nov 1979 A
4181242 Zygiel et al. Jan 1980 A
RE30301 Zygiel Jun 1980 E
4218014 Tracy Aug 1980 A
4222972 Caldwell Sep 1980 A
4237536 Enelow et al. Dec 1980 A
4252253 Shannon Feb 1981 A
4302775 Widergren et al. Nov 1981 A
4333587 Fessler et al. Jun 1982 A
4354613 Desai et al. Oct 1982 A
4377246 McMillin et al. Mar 1983 A
4380046 Frosch Apr 1983 A
4393468 New Jul 1983 A
4413752 McMillin et al. Nov 1983 A
4458584 Annese et al. Jul 1984 A
4466342 Basile et al. Aug 1984 A
4475448 Shoaf et al. Oct 1984 A
4509690 Austin et al. Apr 1985 A
4520950 Jeans Jun 1985 A
4549675 Austin Oct 1985 A
4553573 McGarrah Nov 1985 A
4560089 McMillin et al. Dec 1985 A
4577782 Fessler Mar 1986 A
4578799 Scholl et al. Mar 1986 A
RE32179 Sedam et al. Jun 1986 E
4633386 Terepin et al. Dec 1986 A
4658988 Hassell Apr 1987 A
4694416 Wheeler et al. Sep 1987 A
4711374 Gaunt et al. Dec 1987 A
4713755 Worley, Jr. et al. Dec 1987 A
4719056 Scott Jan 1988 A
4726494 Scott Feb 1988 A
4747516 Baker May 1988 A
4748585 Chiarulli et al. May 1988 A
4758985 Carter Jul 1988 A
4760525 Webb Jul 1988 A
4760544 Lamb Jul 1988 A
4765513 McMillin et al. Aug 1988 A
4766548 Cedrone et al. Aug 1988 A
4781309 Vogel Nov 1988 A
4800492 Johnson et al. Jan 1989 A
4811214 Nosenchuck et al. Mar 1989 A
4824075 Holzboog Apr 1989 A
4827426 Patton et al. May 1989 A
4850269 Hancock et al. Jul 1989 A
4856684 Gerstung Aug 1989 A
4870302 Freeman Sep 1989 A
4901887 Burton Feb 1990 A
4905231 Leung et al. Feb 1990 A
4921315 Metcalfe et al. May 1990 A
4930666 Rudick Jun 1990 A
4932564 Austin et al. Jun 1990 A
4936488 Austin Jun 1990 A
4937019 Scott Jun 1990 A
4960261 Scott et al. Oct 1990 A
4961533 Teller et al. Oct 1990 A
4967340 Dawes Oct 1990 A
4974643 Bennett et al. Dec 1990 A
4982876 Scott Jan 1991 A
4993604 Gaunt et al. Feb 1991 A
5007560 Sassak Apr 1991 A
5021947 Campbell et al. Jun 1991 A
5040106 Maag Aug 1991 A
5044171 Farkas Sep 1991 A
5090015 Dabbish et al. Feb 1992 A
5099418 Pian et al. Mar 1992 A
5129549 Austin Jul 1992 A
5139708 Scott Aug 1992 A
5144166 Camarota et al. Sep 1992 A
5156301 Hassell et al. Oct 1992 A
5156871 Goulet et al. Oct 1992 A
5165023 Gifford Nov 1992 A
5165575 Scott Nov 1992 A
5190083 Gupta et al. Mar 1993 A
5190189 Zimmer et al. Mar 1993 A
5193151 Jain Mar 1993 A
5193718 Hassell et al. Mar 1993 A
5202993 Tarsy et al. Apr 1993 A
5203474 Haynes Apr 1993 A
5212777 Gove May 1993 A
5218240 Camarota et al. Jun 1993 A
5226125 Balmer Jul 1993 A
5239654 Ing-Simmons Aug 1993 A
5240144 Feldman Aug 1993 A
5245227 Furtek et al. Sep 1993 A
5261099 Bigo et al. Nov 1993 A
5263509 Cherry et al. Nov 1993 A
5269442 Vogel Dec 1993 A
5280711 Motta et al. Jan 1994 A
5297400 Benton et al. Mar 1994 A
5301100 Wagner Apr 1994 A
5303846 Shannon Apr 1994 A
5335276 Thompson et al. Aug 1994 A
5336950 Popli et al. Aug 1994 A
5339428 Burmeister et al. Aug 1994 A
5343716 Swanson et al. Sep 1994 A
5361362 Benkeser et al. Nov 1994 A
5368198 Goulet Nov 1994 A
5371896 Gove Dec 1994 A
5379343 Grube et al. Jan 1995 A
5381546 Servi et al. Jan 1995 A
5381550 Jourdenais et al. Jan 1995 A
5388062 Knutson Feb 1995 A
5388212 Grube et al. Feb 1995 A
5392960 Kendt et al. Feb 1995 A
5437395 Bull et al. Aug 1995 A
5450557 Kopp et al. Sep 1995 A
5454406 Rejret et al. Oct 1995 A
5465368 Davidson et al. Nov 1995 A
5471592 Gove Nov 1995 A
5475856 Kogge Dec 1995 A
5479055 Eccles Dec 1995 A
5490165 Blakeney, II et al. Feb 1996 A
5491823 Ruttenberg Feb 1996 A
5507009 Grube et al. Apr 1996 A
5515519 Yoshioka et al. May 1996 A
5517600 Shimokawa May 1996 A
5519694 Brewer et al. May 1996 A
5522070 Sumimoto May 1996 A
5522083 Gove May 1996 A
5530964 Alpert et al. Jun 1996 A
5534796 Edwards Jul 1996 A
5542265 Rutland Aug 1996 A
5553755 Bonewald et al. Sep 1996 A
5555417 Odnert et al. Sep 1996 A
5560028 Sachs et al. Sep 1996 A
5560038 Haddock Sep 1996 A
5570587 Kim Nov 1996 A
5572572 Kawan et al. Nov 1996 A
5590353 Sakakibara et al. Dec 1996 A
5594657 Cantone et al. Jan 1997 A
5600810 Ohkami Feb 1997 A
5600844 Shaw et al. Feb 1997 A
5602833 Zehavi Feb 1997 A
5603043 Taylor et al. Feb 1997 A
5607083 Vogel et al. Mar 1997 A
5608643 Wichter et al. Mar 1997 A
5611867 Cooper et al. Mar 1997 A
5613146 Gove Mar 1997 A
5623545 Childs et al. Apr 1997 A
5625669 McGregor et al. Apr 1997 A
5626407 Westcott May 1997 A
5630206 Urban et al. May 1997 A
5635940 Hickman et al. Jun 1997 A
5646544 Iadanza Jul 1997 A
5646545 Trimberger et al. Jul 1997 A
5647512 Assis Mascarenhas de Oliveira et al. Jul 1997 A
5667110 McCann et al. Sep 1997 A
5684793 Kiema et al. Nov 1997 A
5684980 Casselman Nov 1997 A
5687236 Moskowitz et al. Nov 1997 A
5694613 Suzuki Dec 1997 A
5694794 Jerg et al. Dec 1997 A
5696913 Gove Dec 1997 A
5699328 Ishizaki et al. Dec 1997 A
5701398 Glier et al. Dec 1997 A
5701482 Harrison et al. Dec 1997 A
5704053 Santhanam Dec 1997 A
5706191 Bassett et al. Jan 1998 A
5706976 Purkey Jan 1998 A
5712996 Schepers Jan 1998 A
5720002 Wang Feb 1998 A
5721693 Song Feb 1998 A
5721854 Ebicioglu et al. Feb 1998 A
5729754 Estes Mar 1998 A
5732563 Bethuy et al. Mar 1998 A
5734808 Takeda Mar 1998 A
5737631 Trimberger Apr 1998 A
5742180 DeHon et al. Apr 1998 A
5742821 Prasanna Apr 1998 A
5745366 Highma et al. Apr 1998 A
RE35780 Hassell et al. May 1998 E
5751295 Becklund et al. May 1998 A
5754227 Fukuoka May 1998 A
5758261 Wiedeman May 1998 A
5768561 Wise Jun 1998 A
5768609 Gove Jun 1998 A
5778439 Trimberger et al. Jul 1998 A
5784636 Rupp Jul 1998 A
5787237 Reilly Jul 1998 A
5790817 Asghar et al. Aug 1998 A
5791517 Avital Aug 1998 A
5791523 Oh Aug 1998 A
5794062 Baxter Aug 1998 A
5794067 Kadowaki Aug 1998 A
5802055 Krein et al. Sep 1998 A
5818603 Motoyama Oct 1998 A
5822308 Weigand et al. Oct 1998 A
5822313 Malek et al. Oct 1998 A
5822360 Lee et al. Oct 1998 A
5828858 Athanas et al. Oct 1998 A
5829085 Jerg et al. Nov 1998 A
5835753 Witt Nov 1998 A
5838165 Chatter Nov 1998 A
5845815 Vogel Dec 1998 A
5860021 Klingman Jan 1999 A
5862961 Motta et al. Jan 1999 A
5870427 Tiedemann, Jr. et al. Feb 1999 A
5873045 Lee et al. Feb 1999 A
5881106 Cartier Mar 1999 A
5884284 Peters et al. Mar 1999 A
5886537 Macias et al. Mar 1999 A
5887174 Simons et al. Mar 1999 A
5889816 Agrawal et al. Mar 1999 A
5890014 Long Mar 1999 A
5892900 Ginter et al. Apr 1999 A
5892961 Trimberger Apr 1999 A
5892962 Cloutier Apr 1999 A
5894473 Dent Apr 1999 A
5901884 Goulet et al. May 1999 A
5903886 Heimlich et al. May 1999 A
5907285 Toms et al. May 1999 A
5907580 Cummings May 1999 A
5910733 Bertolet et al. Jun 1999 A
5912572 Graf, III Jun 1999 A
5913172 McCabe et al. Jun 1999 A
5917852 Butterfield et al. Jun 1999 A
5920801 Thomas et al. Jul 1999 A
5931918 Row et al. Aug 1999 A
5933642 Greenbaum et al. Aug 1999 A
5940438 Poon et al. Aug 1999 A
5949415 Lin et al. Sep 1999 A
5950011 Albrecht et al. Sep 1999 A
5950131 Vilmur Sep 1999 A
5951674 Moreno Sep 1999 A
5953322 Kimball Sep 1999 A
5956518 DeHon et al. Sep 1999 A
5956967 Kim Sep 1999 A
5959811 Richardson Sep 1999 A
5959881 Trimberger et al. Sep 1999 A
5963048 Harrison et al. Oct 1999 A
5966534 Cooke et al. Oct 1999 A
5970254 Cooke et al. Oct 1999 A
5987105 Jenkins et al. Nov 1999 A
5987611 Freund Nov 1999 A
5991302 Berl et al. Nov 1999 A
5991308 Fuhrmann et al. Nov 1999 A
5993739 Lyon Nov 1999 A
5999734 Willis et al. Dec 1999 A
6005943 Cohen et al. Dec 1999 A
6006249 Leong Dec 1999 A
6016395 Mohamed Jan 2000 A
6021186 Suzuki et al. Feb 2000 A
6021492 May Feb 2000 A
6023742 Ebeling et al. Feb 2000 A
6023755 Casselman Feb 2000 A
6028610 Deering Feb 2000 A
6036166 Olson Mar 2000 A
6039219 Bach et al. Mar 2000 A
6041322 Meng et al. Mar 2000 A
6041970 Vogel Mar 2000 A
6046603 New Apr 2000 A
6047115 Mohan et al. Apr 2000 A
6052600 Fette et al. Apr 2000 A
6055314 Spies et al. Apr 2000 A
6056194 Kolls May 2000 A
6059840 Click, Jr. May 2000 A
6061580 Altschul et al. May 2000 A
6070003 Gove May 2000 A
6073132 Gehman Jun 2000 A
6076174 Freund Jun 2000 A
6078736 Guccione Jun 2000 A
6085740 Ivri et al. Jul 2000 A
6088043 Kelleher et al. Jul 2000 A
6091263 New et al. Jul 2000 A
6091765 Pietzold, III et al. Jul 2000 A
6094065 Tavana et al. Jul 2000 A
6094726 Gonion et al. Jul 2000 A
6111893 Volftsun et al. Aug 2000 A
6111935 Hughes-Hartogs Aug 2000 A
6115751 Tam et al. Sep 2000 A
6119178 Martin et al. Sep 2000 A
6120551 Law et al. Sep 2000 A
6122670 Bennett et al. Sep 2000 A
6128307 Brown Oct 2000 A
6134605 Hudson et al. Oct 2000 A
6138693 Matz Oct 2000 A
6141283 Bogin et al. Oct 2000 A
6150838 Wittig et al. Nov 2000 A
6154494 Sugahara et al. Nov 2000 A
6157997 Oowaki et al. Dec 2000 A
6173389 Pechanek et al. Jan 2001 B1
6175854 Bretscher Jan 2001 B1
6175892 Sazzad et al. Jan 2001 B1
6181981 Varga et al. Jan 2001 B1
6185418 MacLellan et al. Feb 2001 B1
6192070 Poon et al. Feb 2001 B1
6192255 Lewis et al. Feb 2001 B1
6192388 Cajolet Feb 2001 B1
6195788 Leaver et al. Feb 2001 B1
6198924 Ishii et al. Mar 2001 B1
6199181 Rechef et al. Mar 2001 B1
6202130 Scales, III et al. Mar 2001 B1
6202189 Hinedi et al. Mar 2001 B1
6219697 Lawande et al. Apr 2001 B1
6219756 Kasamizugami Apr 2001 B1
6219780 Lipasti Apr 2001 B1
6223222 Fijolek et al. Apr 2001 B1
6226387 Tewfik et al. May 2001 B1
6230307 Davis et al. May 2001 B1
6237029 Master et al. May 2001 B1
6246883 Lee Jun 2001 B1
6247125 Noel-Baron et al. Jun 2001 B1
6249251 Chang et al. Jun 2001 B1
6258725 Lee et al. Jul 2001 B1
6260088 Gove Jul 2001 B1
6263057 Silverman Jul 2001 B1
6266760 DeHon et al. Jul 2001 B1
6272579 Lentz et al. Aug 2001 B1
6272616 Fernando et al. Aug 2001 B1
6281703 Furuta et al. Aug 2001 B1
6282627 Wong et al. Aug 2001 B1
6289375 Knight et al. Sep 2001 B1
6289434 Roy Sep 2001 B1
6289488 Dave et al. Sep 2001 B1
6292822 Hardwick Sep 2001 B1
6292827 Raz Sep 2001 B1
6292830 Taylor et al. Sep 2001 B1
6301653 Mohamed et al. Oct 2001 B1
6305014 Roediger et al. Oct 2001 B1
6311149 Ryan et al. Oct 2001 B1
6321985 Kolls Nov 2001 B1
6326806 Fallside et al. Dec 2001 B1
6346824 New Feb 2002 B1
6347346 Taylor Feb 2002 B1
6349394 Brock et al. Feb 2002 B1
6353841 Marshall et al. Mar 2002 B1
6356994 Barry et al. Mar 2002 B1
6359248 Mardi Mar 2002 B1
6360256 Lim Mar 2002 B1
6360259 Bradley Mar 2002 B1
6360263 Kurtzberg et al. Mar 2002 B1
6363411 Dugan et al. Mar 2002 B1
6366999 Drabenstott et al. Apr 2002 B1
6377983 Cohen et al. Apr 2002 B1
6378072 Collins et al. Apr 2002 B1
6381293 Lee et al. Apr 2002 B1
6381735 Hunt Apr 2002 B1
6385751 Wolf May 2002 B1
6405214 Meade, II Jun 2002 B1
6408039 Ito Jun 2002 B1
6410941 Taylor et al. Jun 2002 B1
6411612 Halford et al. Jun 2002 B1
6421372 Bierly et al. Jul 2002 B1
6421809 Wuytack et al. Jul 2002 B1
6426649 Fu et al. Jul 2002 B1
6430624 Jamtgaard et al. Aug 2002 B1
6433578 Wasson Aug 2002 B1
6434590 Blelloch et al. Aug 2002 B1
6438737 Morelli et al. Aug 2002 B1
6456996 Crawford, Jr. et al. Sep 2002 B1
6459883 Subramanian et al. Oct 2002 B2
6467009 Winegarden et al. Oct 2002 B1
6469540 Nakaya Oct 2002 B2
6473609 Schwartz et al. Oct 2002 B1
6483343 Faith et al. Nov 2002 B1
6507947 Schreiber et al. Jan 2003 B1
6510138 Pannell Jan 2003 B1
6510510 Garde Jan 2003 B1
6526430 Hung et al. Feb 2003 B1
6538470 Langhammer et al. Mar 2003 B1
6556044 Langhammer et al. Apr 2003 B2
6563891 Eriksson et al. May 2003 B1
6570877 Kloth et al. May 2003 B1
6577678 Scheuermann Jun 2003 B2
6587684 Hsu et al. Jul 2003 B1
6590415 Agrawal et al. Jul 2003 B2
6601086 Howard et al. Jul 2003 B1
6601158 Abbott et al. Jul 2003 B1
6604085 Kolls Aug 2003 B1
6604189 Zemlyak et al. Aug 2003 B1
6606529 Crowder, Jr. et al. Aug 2003 B1
6615333 Hoogerbrugge et al. Sep 2003 B1
6618434 Heidari-Bateni et al. Sep 2003 B2
6640304 Ginter et al. Oct 2003 B2
6647429 Semal Nov 2003 B1
6653859 Sihlbom et al. Nov 2003 B2
6675265 Barroso et al. Jan 2004 B2
6675284 Warren Jan 2004 B1
6691148 Zinky et al. Feb 2004 B1
6694380 Wolrich et al. Feb 2004 B1
6711617 Bantz et al. Mar 2004 B1
6718182 Kung Apr 2004 B1
6721286 Williams et al. Apr 2004 B1
6721884 De Oliveira Kastrup Pereira et al. Apr 2004 B1
6732354 Ebeling et al. May 2004 B2
6735621 Yoakum et al. May 2004 B1
6738744 Kirovski et al. May 2004 B2
6748360 Pitman et al. Jun 2004 B2
6751723 Kundu et al. Jun 2004 B1
6754470 Hendrickson et al. Jun 2004 B2
6760587 Holtzman et al. Jul 2004 B2
6760833 Dowling Jul 2004 B1
6766165 Sharma et al. Jul 2004 B2
6778212 Deng et al. Aug 2004 B1
6785341 Walton et al. Aug 2004 B2
6819140 Yamanaka et al. Nov 2004 B2
6823448 Roth et al. Nov 2004 B2
6829633 Gelfer et al. Dec 2004 B2
6832250 Coons et al. Dec 2004 B1
6836839 Master et al. Dec 2004 B2
6859434 Segal et al. Feb 2005 B2
6865664 Budrovic et al. Mar 2005 B2
6871236 Fishman et al. Mar 2005 B2
6883084 Donohoe Apr 2005 B1
6894996 Lee May 2005 B2
6901440 Bimm et al. May 2005 B1
6912515 Jackson et al. Jun 2005 B2
6941336 Mar Sep 2005 B1
6980515 Schunk et al. Dec 2005 B1
6985517 Matsumoto et al. Jan 2006 B2
6986021 Master et al. Jan 2006 B2
6986142 Ehlig et al. Jan 2006 B1
6988139 Jervis et al. Jan 2006 B1
6989021 Bosma et al. Jan 2006 B2
7032229 Flores et al. Apr 2006 B1
7044741 Leem May 2006 B2
7082456 Mani-Meitav et al. Jul 2006 B2
7139910 Ainsworth et al. Nov 2006 B1
7142731 Toi Nov 2006 B1
7249242 Ramchandran Jul 2007 B2
20010003191 Kovacs et al. Jun 2001 A1
20010023482 Wray Sep 2001 A1
20010029515 Mirsky Oct 2001 A1
20010034795 Moulton et al. Oct 2001 A1
20010039654 Miyamoto Nov 2001 A1
20010048713 Medlock et al. Dec 2001 A1
20010048714 Jha Dec 2001 A1
20010050948 Ramberg et al. Dec 2001 A1
20020010848 Kamano et al. Jan 2002 A1
20020013799 Blaker Jan 2002 A1
20020013937 Ostanevich et al. Jan 2002 A1
20020015435 Rieken Feb 2002 A1
20020015439 Kohli et al. Feb 2002 A1
20020023210 Tuomenoksa et al. Feb 2002 A1
20020024942 Tsuneki et al. Feb 2002 A1
20020024993 Subramanian et al. Feb 2002 A1
20020031166 Subramanian et al. Mar 2002 A1
20020032551 Zakiya Mar 2002 A1
20020035623 Lawande et al. Mar 2002 A1
20020041581 Aramaki Apr 2002 A1
20020042907 Yamanaka et al. Apr 2002 A1
20020061741 Leung et al. May 2002 A1
20020069282 Reisman Jun 2002 A1
20020072830 Hunt Jun 2002 A1
20020078337 Moreau et al. Jun 2002 A1
20020083305 Renard et al. Jun 2002 A1
20020083423 Ostanevich et al. Jun 2002 A1
20020087829 Snyder et al. Jul 2002 A1
20020089348 Langhammer Jul 2002 A1
20020101909 Chen et al. Aug 2002 A1
20020107905 Roe et al. Aug 2002 A1
20020107962 Richter et al. Aug 2002 A1
20020119803 Bitterlich et al. Aug 2002 A1
20020120672 Butt et al. Aug 2002 A1
20020133688 Lee et al. Sep 2002 A1
20020138716 Master et al. Sep 2002 A1
20020141489 Imaizumi Oct 2002 A1
20020147845 Sanchez-Herrero et al. Oct 2002 A1
20020159503 Ramachandran Oct 2002 A1
20020162026 Neuman et al. Oct 2002 A1
20020168018 Scheuermann Nov 2002 A1
20020181559 Heidari-Bateni et al. Dec 2002 A1
20020184275 Dutta et al. Dec 2002 A1
20020184291 Hogenauer Dec 2002 A1
20020184498 Qi Dec 2002 A1
20020191790 Anand et al. Dec 2002 A1
20030007606 Suder et al. Jan 2003 A1
20030012270 Zhou et al. Jan 2003 A1
20030018446 Makowski et al. Jan 2003 A1
20030018700 Giroti et al. Jan 2003 A1
20030023830 Hogenauer Jan 2003 A1
20030026242 Jokinen et al. Feb 2003 A1
20030030004 Dixon et al. Feb 2003 A1
20030046421 Horvitz et al. Mar 2003 A1
20030061260 Rajkumar Mar 2003 A1
20030061311 Lo Mar 2003 A1
20030063656 Rao et al. Apr 2003 A1
20030074473 Pham et al. Apr 2003 A1
20030076815 Miller et al. Apr 2003 A1
20030099223 Chang et al. May 2003 A1
20030102889 Master et al. Jun 2003 A1
20030105949 Master et al. Jun 2003 A1
20030110485 Lu et al. Jun 2003 A1
20030142818 Raghunathan et al. Jul 2003 A1
20030154357 Master et al. Aug 2003 A1
20030163723 Kozuch et al. Aug 2003 A1
20030172138 McCormack et al. Sep 2003 A1
20030172139 Srinivasan et al. Sep 2003 A1
20030200538 Ebeling et al. Oct 2003 A1
20030212684 Meyer et al. Nov 2003 A1
20030229864 Watkins Dec 2003 A1
20040006584 Vandeweerd Jan 2004 A1
20040010645 Scheuermann et al. Jan 2004 A1
20040015970 Scheuermann Jan 2004 A1
20040025159 Scheuermann et al. Feb 2004 A1
20040057505 Valio Mar 2004 A1
20040062300 McDonough et al. Apr 2004 A1
20040081248 Parolari Apr 2004 A1
20040093479 Ramchandran May 2004 A1
20040168044 Ramchandran Aug 2004 A1
20050044344 Stevens Feb 2005 A1
20050166038 Wang et al. Jul 2005 A1
20050198199 Dowling Sep 2005 A1
20060031660 Master et al. Feb 2006 A1
Foreign Referenced Citations (52)
Number Date Country
100 18 374 Oct 2001 DE
0 301 169 Feb 1989 EP
0 166 586 Jan 1991 EP
0 236 633 May 1991 EP
0 478 624 Apr 1992 EP
0 479 102 Apr 1992 EP
0 661 831 Jul 1995 EP
0 668 659 Aug 1995 EP
0 690 588 Jan 1996 EP
0 691 754 Jan 1996 EP
0 768 602 Apr 1997 EP
0 817 003 Jan 1998 EP
0 821 495 Jan 1998 EP
0 866 210 Sep 1998 EP
0 923 247 Jun 1999 EP
0 926 596 Jun 1999 EP
1 056 217 Nov 2000 EP
1 061 437 Dec 2000 EP
1 061 443 Dec 2000 EP
1 126 368 Aug 2001 EP
1 150 506 Oct 2001 EP
1 189 358 Mar 2002 EP
2 067 800 Jul 1981 GB
2 237 908 May 1991 GB
62-249456 Oct 1987 JP
63-147258 Jun 1988 JP
4-51546 Feb 1992 JP
7-064789 Mar 1995 JP
7066718 Mar 1995 JP
10233676 Sep 1998 JP
10254696 Sep 1998 JP
11296345 Oct 1999 JP
2000315731 Nov 2000 JP
2001-053703 Feb 2001 JP
WO 8905029 Jun 1989 WO
WO 8911443 Nov 1989 WO
WO 9100238 Jan 1991 WO
WO 9313603 Jul 1993 WO
WO 9511855 May 1995 WO
WO 9633558 Oct 1996 WO
WO 9832071 Jul 1998 WO
WO 9903776 Jan 1999 WO
WO 9921094 Apr 1999 WO
WO 9926860 Jun 1999 WO
WO 9965818 Dec 1999 WO
WO 0019311 Apr 2000 WO
WO 0065855 Nov 2000 WO
WO 0069073 Nov 2000 WO
WO 0111281 Feb 2001 WO
WO 0122235 Mar 2001 WO
WO 0176129 Oct 2001 WO
WO 0212978 Feb 2002 WO
Non-Patent Literature Citations (129)
Entry
Abnous et al, “Ultra-Low-Power Domain-Specific Multimedia Processors,” VLSI Signal Processing, IX, 1998, IEEE Workshop in San Francisco, Ca, USA, Oct. 30-Nov. 1, 1998, pp. 461-470 (Oct. 30, 1998).
Aggarwal et al., “Efficient I Iuffman Decoding,” International Conference on Image Processing IEEE 1:936-939 (Sep. 10-13, 2000).
Allan et at, “Software Pipelining,” ACM Computing Surveys, 27(3):1-78 (Sep. 1995).
Alsolaim et al., “Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems,” Field Programmable Custom Computing Machines, 2000 IEEE Symposium, Napa Valley, Los Alamitos, Ca. IEEE Comput. Soc. pp. 205-214 (Apr. 17-19, 2000).
Ashenden et al, “The VHDL Cookbook,” Dept. Computer Science, University of Adelaide, South Australia. Downloaded from http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf on Dec. 7, 2006 (Jul. 1990).
Bacon et al., “Compiler Transformations for High-Performance Computing,” ACM Computing Surveys 26(4):368-373 (Dec. 1994).
Balasubramonian et al., “Reducing the Complexity of the Register File in Dynamic Superscalar Processors,” Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture, pp. 237-248 (Dec. 1, 2001).
Banerjee et al., “A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems,” 2000 IEEE Symposium, pp. 39-48, (Apr. 17-19, 2000).
Bapte et al., “Uniform Execution Environment for Dynamic Reconfiguration,” Darpa Adaptive Computing Systems, http://isis.vanderbilt.edu/publications/archive/babty—T—#—0—1999—Uniform—Ex.pdf, pp. 1-7 (1999).
Baumgarte et al., “PACT XPP—A Self-Reconfigurable Data Processing Architecture,” NN www.pactcorp.com/sneu/download/ersa01.pdf; retrieved on Nov. 25, 2005 (Jun. 25, 2001).
Becker ct al., “An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing,” IEEE Conference Proceedings Article pp. 341-346 (Sep. 18, 2000).
Becker et al., “Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture,” VLSI 2001, Proceedings IEEE Computer Soc. Workshop, Piscataway, NJ, USA, pp. 41-46 (Apr. 19-20, 2001).
Bevstar, BevStar Bottled Water Model Advertisement Automatic Merchandiser at www.AMonline.com (2005).
Bevstar, BevStar Point of Use Water Model Advertisement Automatic Merchandiser at www.AMonline.com (2005).
Bishop & Loucks, “A Heterogeneous Environment for Hardware/Software Cosimulation,” Proceedings of the 30th Annual Simulation Symposium, pp. 14-22 (Apr. 7-9, 1997).
Brakensiek et al., “Re-Configurable Multi-Standard Terminal for Heterogeneous Networks,” Radio and Wireless Conference, Rawcon 2002 IEEE. pp. 27-30 (2002).
Brown et al., “Quick PDA Data Exchange,” PC Magazine pp. 1-3 (May 22, 2001).
Buck et al., “Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems,” International Journal of Computer Simulation 4:155-182 (Apr. 1994).
Burns et al., “A Dynamic Reconfiguration Run-Time System,” Proceedings of the 5th Annual Symposium on Field-Programmable Custom Computing Machines, pp. 1 66-75 (Apr. 16, 1997).
Business Wire, “Whirlpool Internet-Enabled Appliances to Use Beeline Shopper Software Features,” http://www.whirlpoocorp.com/news/releases/release.asp?rid=90 (Feb. 16, 2001).
Buttazzo et al., “Optimal Deadline Assignment for Scheduling Soft Aperiodic Tasks in Hard Real-Time Environments,” Engineering of Complex Computer Systems, Proceedings of the Third IEEE International Conference on Como, pp. 39-48 (Sep. 8, 1997).
Callahan et al., “Adapting Software Pipelining for Reconfigurable Computing,” in Proceedings of the International Conference on Compilers, Architectrue and Synthesis for Embedded Systems p. 8, ACM (CASES '00, San Jose, CA) (Nov. 17-18, 2000).
Chapman & Mehrotra, “OpenMP and HPF: Integrating Two Paradigms,” Proceedings of the 4th International Euro-Par Conference (Euro-Par'98), Springer-Verlag I Ieidelberg, Lecture Notes in Computer Science 1470:650-658 (1998).
Chen et al., “A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths,” IEEE Journal of Solid-State Circuits, IEEE 35:74-75 (Feb. 1, 2001).
Clarke, “Embedded Solutions Enters Development Pact with Marconi,” EETimes Online (Jan. 26, 2000).
Compton & Hauck, “Reconfigurable Computing: A Survey of Systems and Software,” ACM Press, ACM Computing Surveys (CSUR) 34(2):171-210 (Jun. 2002).
Compton et al., “Configuration Relocation and Defragmentation for Run-Time Reconfigurable Computing,” Northwestern University, http://citeseer.nj.nec.com/compton00configuration.html, pp. 1-17 (2000).
Conte et al., “Dynamic Rescheduling: A Technique for Object Code Compatibility in VLIW Architectures,” Proceedings of the 28th Annulal International Symposium on Microarchitecture pp. 208-218 (Nov. 29, 1995).
Conte et al., “Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings,” Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 29:201-211 (Dec. 2, 1996).
Cray Research Inc., “Cray T3E Fortran Optimization Guide,” Ver. 004-2518-002, Section 4.5 (Jan. 1999).
Cummings et al., “FPGA in the Software Radio,” IEEE Communications Magazine . 37(2):108-112 (Feb. 1999).
Dandalis et al., “An Adaptive Cryptograhic Engine for IPSec Architectures,” IEEE pp. 132-141 (Jan. 2000).
David et al., “DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunication Constraints,” Proceedings of the International Parallel and Distributed Processing Symposium pp. 156-163 (Apr. 15, 2002).
Deepakumara et al., “FPGA Implementation of MD5 has Algorithm,” Canadian Conference on Electrical and Computer Engineering, IEEE (2001).
Dehon et al., “Reconfigurable Computing: What, Why and Implications for Design Automation,” Design Automation Conference Proceedings pp. 610-615 (1999).
Dipert, “Figuring Out Reconfigurable Logic,” EDN 44(16):107-114 (Aug. 5, 1999).
Dominikus, “A Hardware Implementation of MD4-Family Hash Algorithms,” 9th International Conference on Electronics, Circuits and Systems IEEE (2002).
Dorband, “aCe C Language Reference Guide,” Online (Archived Mar. 2001), http://web.archive.org/web/20000616053819/http://newton.gsfc.nasa.gov/aCe/aCe—dir/aCe—cc—Ref.html (Mar. 2001).
Drozdowski, “Scheduling Multiprocessor Tasks—An Overview,” Instytut Informatyki Politechnika, pp. 1-31 (Jan. 31, 1996).
Ebeling et al., “RaPiD Reconfigurable Pipelined Datapath,” Springer-Verlag, 6th International Workshop on Field-Programmable Logic and Applications pp. 126-135 (1996).
Fawer et al., “A Multiprocessor Approach for Implementing a Time-Diversity Spread Specturm Receiver,” Proceeding sof the 1990 International Zurich Seminal on Digital Communications, pp. 173-180 (Mar. 5-8, 1990).
Fisher, “Gone Flat,” Forbes pp. 76-79 (Oct. 2001).
Fleischmann et al., “Prototyping Networked Embedded Systems,” Integrated Engineering, pp. 116-119 (Feb. 1999).
Forbes “ Best of the Web—Computer Networking/Consumer Durables,” The Forbes Magnetic 40 p. 80 (May 2001).
Gibson, “Fresh Technologies Will Create Myriad Functions,” FT Information Technology Review; World Wide Web at http://technews.acm.org/articles/2000-2/0301w.html?searchterm=%22fresh+technologies%22 (Mar. 1, 2000).
Gluth, “Integrierte Signalprozessoren,” Elektronik 35(18):112-118 Franzis Verlag GMBH, Munich, Germany (Sep. 5, 1986).
Gokhale & Schlesinger, “A Data Parallel C and Its Platforms,” Proceedings of the Fifth Symposium on the Frontiers of Massively Parallel Computation pp. 194-202 (Frontiers '95) (Feb. 1995).
Grimm et al., “A System Architecture for Pervasive Computing,” Washington University, pp. 1-6 (Sep. 2000).
Halbwachs et al., “The Synchronous Data Flow Programming Language LUSTRE,” Proceedings of the IEEE 79(9):1305-1319 (Sep. 1991).
Hammes et al., “Cameron: High Level Language Compilation for Reconfigurable Systems,” Proc. of the Intl. Conf. on Parallel Architectures and Compilation Techniques, pp. 236-244 (Oct. 1999).
Hartenstein, “Coarse Grain Reconfigurable Architectures,” Design Automation Conference, 2001. Proceedings of the ASP-Dac 2001, Asian and South Pacific Jan. 30, 2001- Feb. 2, 2001, Piscataway, NJ, US, IEEE, pp. 564-569 (Jan. 30, 2001).
Heinz, “An Efficiently Compilable Extension of {M} odula-3 for Problem-Oriented Explicitly Parallel Programming,” Proceedings of the Joint Symposium on Parallel Processing (May 1993).
Hinden et al., “The DARPA Internet: Interconnecting Heterogeneous Computer Networks with Gateways,” IEEE Computer Magazine pp. 38-48 (1983).
Horton, “Beginning Java 2: JDK 1.3 Edition,” Wrox Press, Chapter 8, pp. 313-316 (Feb. 2001).
Huff et al., “Lifetime-Sensitive Modulo Scheduling,” 6th Conference on Programming Language, Design and Implementation, pp. 258-267, ACM (1993).
IBM, “Multisequencing a Single Instruction Stream Scheduling with Space-time Trade-offs,” IBM Technical Disclosure Bulletin 36(2):105-108 (Feb. 1, 1993).
IEEE, “IEEE Standard Verilog Hardware Description Language,” downloaded from http://inst.eecs.berkeley.edu/˜cs150/fa06/Labs/verilog-ieee.pdf on Dec. 7, 2006 (Sep. 2001).
Internet Wire, Sunbeam Joins Microsoft in University Plug and Play Forum to Establish a “Universal” Smart Appliance Technology Standard (Mar. 23, 2000).
Ishii et al., “Parallel Variable Length Decoding with Inverse Quantization for Software MPEG-2 Decoders,” Workshop on Signal Processing Systems, Design and Implementation, IEEE pp. 500-509 (Nov. 3-5, 1997).
Isoworth, “Isoworth Beverage Dispensing Technology Worldwide Company,” Brochure (May 22, 2000).
Jain et al., “An Alternative Approach Towards the Design of Control Units,” Microelectronics and Reliability 24(6):1009-1012 (1984).
Jain, “Parallel Processing with the TMS320C40 Parallel Digital Signal Processor,” Sonitech International Inc., pp. 13-46. Retrieved from: http.//www-s.ti.com/sc/psheets/spra031/spra031.pdf retrieved on Apr. 14, 2004 (Feb. 1994).
Janssen et al., “Partitioned Register File for TTAs,” Proceedings of the 28th Annual International Symposium on Microarchitecture, pp. 303-312 (Nov. 1995).
Jong-Pyng et al., “Real-Time Virtual Channel Flow Control,” Proceedings of the Annual International Phoenix Conference on Computers and Communications, Conf. 13, pp. 97-103 (Apr. 12, 1994).
Jung et al., “Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design,” Proceedings of the 13th International Symposium on System Synthesis pp. 79-84 (ISSS'00) (Sep. 2000).
Kaufmann et al., “Digital Spread-Spectrum Multipath-Diversity Receiver for Indoor Communication,” from Pioneers to the 21st Century; Denver, Proceedings of the Vehicular Technology Socity [sic] Conference, NY, IEEE, US 2(Conf. 42):1038-1041 (May 10-13, 1992).
Kneip et al., “An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor,” Journal of VLSI Signal Processing Systems for Signal, Image, an dVideo Technology 16(1):31-40 (May 1, 1997).
Lee & Messerschmitt, “Pipeline Interleaved Programmable DSP's: Synchronous Data Flow Programming,” IEEE Transactions on Acoustics, Speech, and Signal Processing ASSP-35(9):1334-1345 (Sep. 1987).
Lee & Messerschmitt, “Synchronous Data Flow,” Proceedings of the IEEE 75(9):1235-1245 (Sep. 1987).
Lee & Parks, “Dataflow Process Networks,” Proceedings of the IEEE 83(5):773-799 (May 1995).
Liu et al., “Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment,” Journal of the Association for Computing 20(1):46-61 (1973).
Llosa et al., “Lifetime-Sensitive Modulo Scheduling in a Production Environment,” IEEE Trans. on Comps. 50(3):234-249 (Mar. 2001).
Lu et al., “The Morphosys Dynamically Reconfigurable System-On-Chip,” Proceedings of the First NASA/ DOD Workshop on Evolvable Hardware, pp. 152-160 (Jul. 19, 1999).
Mangione-Smith et al., “Seeking Solutions in Configurable Computing,” Computer 30(12):38-43 (Dec. 1997).
Manion, “Network CPU Adds Spice,” Electronic Engineering Times, Issue 1126 (Aug. 14, 2000).
Mascia & Ishii., “Neural Net Implementation on Single-Chip Digital Signal Processor,” IEEE (1989).
McGraw, “Parallel Functional Programming in Sisal: Fictions, Facts, and Future,” Lawrence Livermore National Laboratory pp. 1-40 (Jul. 1993).
Najjar et al., “High-Level Language Abstraction for Reconfigurable Computing,” Computer 36(8):63-69 (Aug. 2003).
Nichols et al., “Data Management and Control-Flow Constructs in a SIMD/SPMD Parallel Language/Compiler,” Proceedings of the 3rd Symposium on the Frontiers of Massively Parallel Computation pp. 397-406 (Oct. 1990).
OpenMP Architecture Review Board, “OpenMP C and C++ Application Program Interface,” pp. 7-16 (Oct. 1998).
Oracle Corporation, “Oracle8i JDBC Developer's Guide and Reference,” Release 3, 8.1.7, pp. 10-8-10-10 (Jul. 2000).
Pauer et al., “Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results,” Proc. IEEE Symposium on FPGA's for Custom Computing Machines (FCCM), Napa CA (1999).
Pauer et al., “Algorithm Analysis and Mapping Environment for Adaptive Computing Systems,” Presentation slides, Third Bi-annual Ptolemy Miniconference (1999).
Ramamritham et al., “On Scheduling Algorithms for Real-Time Multiprocessor Systems,” Algorithms and Applications, Proceedings of the International conference on Parallel Processing 3:143-152 (Aug. 8, 1989).
Schneider, “A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders,” Proceedings of the Design Automation Conference 34:498-503 (Jun. 9-13, 1997).
Sidhu et al., “A Self-Reconfigurable Gate Array Architecture,” 10 International Workshop on Field Programmable Logic and Applications http://coblitz.codeen.org.3125/citeseer.ist.psu.edu/cache/papers/cs/17524/http:zSzzSzmaarcii.usc.eduzSzPublicationsZSzsidhu—fp100.pdf/sidhu00selfreconfigurable.pdf retrieved on Jun. 21, 2006 (Sep. 1, 2001).
Smith, “Intro to ASICs: ASIC Cell Libraries,” at http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.5.htm, printed on Feb. 4, 2005 (Jun. 1997).
Souza, “Computing's New Face—Reconfigurable Devices Could Rattle Supply Chain,” Electronic Buyers' News Issue 1205, p. P.1 (Apr. 3, 2000).
Souza, “Quicksilver Buys White Eagle,” Electronic Buyers News, Issue 1220 (Jul. 17, 2000).
Sriram et al., “MPEG-2 Video Decoding on the TMS320C6X DSP Architecture,” Conference Record of the 32nd Asilomar Conference on Signals, Systems, and Computers, IEEE pp. 1735-1739 (Nov. 1-4, 1998).
Steiner, “Coke Chief's Latest Daft Idea—A Cola Tap in Every House,” Sunday Times (Mar. 2001).
Sun Microsystems, “FORTRAN 3.0.1 User's Guide, Revision A,” pp. 57-68 (Aug. 1994).
Svensson, “Co's Join on Home Web Wiring Network,” Associated Press Online printed on Apr. 30, 2008 (Jun. 2000).
Tang et al., “Thread Partitioning and Scheduling Based on Cost Model,” Proceedings of the Ninth Annual ACM Symposium on Parallel Algorithms and Architectures, pp. 272-281 Retrieved from: http://doi.acm.org/10.1145/258492.2585 retrieved on Aug. 25, 2004 (1997).
Vaya, “VITURBO: A Reconfigurable Architecture for Ubiquitous Wireless Networks,” A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree Master of Science; RICE University (Aug. 2002).
Wang et al., “Cell Search in W-CDMA,” IEEE Journal on Selected Areas in Communications 18(8):1470-1482 (Aug. 2000).
Wardell, “Help for Hurried Cooks?,” Popular Science, p. 32 (May 2000).
Whiting & Pascoe, “A History of Data-Flow Languages,” IEEE Annals of the History of Computing 16(4):38-59 (1994).
Williamson & Lee, “Synthesis of Parallel Hardware Implementations from Synchronous Dataflow Graph Specifications,” Conference Record of the Thirtieth Asilomar Conference on Signals, Systems and Computers 1340-1343 (Nov. 1996).
Wirthlin et al., “A Dynamic Instruction Set Computer,” Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, pp. 99-107 (Apr. 21, 1995).
www.appliancemagazine.com, World Wide Web at http://web.archive.org/web/20000511085402/http://www.appliancemagazine.com/ printed on Apr. 30, 2008.
www.bestrom.com, BreakMateTM from www.bestrom.com printed on Apr. 29, 2008.
www.beverageexpress.com, Beverage Express from www.beverageexpress.com printed on Apr. 30, 2008.
www.bevstar.com, Isoworth Beverage Dispensing Technology Worldwide from www.bevstar.com printed on Apr. 30, 2008.
www.bonator.com, from the World Wide Web at http://web.archive.org/web/20000510102440/http://www.bonator.com/ printed on Apr. 30, 2008.
www.ecommerce.dewpointinc.com, Swiss Mountain Coffees from www.ecommerce.dewpointinc.com printed on Apr. 30, 2008.
www.gateway.com, World Wide Web, http: //web.archive.org/web/20000229192734/www.gateway.com/productpages/9300splash/index.shtml Available on Mar. 3, 2000, 1 page. (Mar. 3, 2000).
www.icl.com, from the World Wide Web at http://www.icl.com printed on Apr. 30, 2008.
www.margherita2000.com; from Margherita2000.com printed Apr. 30, 2008 (Jan. 26, 2001).
www.sodaclubenterprises.com, Soda-Club Enterprises from www.sodaclubenterprises.com printed on Apr. 30, 2008.
www.symbol.com, Symbol from www.symbol.com printed on Apr. 30, 2008.
www.wunderbar.com, Wunder-Bar Dispensing Systems from www.wunderbar.com printed on Apr. 30, 2008.
Xilinx, “Virtex-II Pro Platform FPGAs: Functional Description DS083-2 (v2.5),” Product Specification, pp. 13-46 (Jan. 20, 2003).
Young, “Architecture Powers up IPSec, SSL,” EETimes, Los Gatos, CA, pp. 1-4 http://www.eetimes.com/story/OEG20011102S0065 (Nov. 2, 2001).
Yuan et al., “A Decomposition Approach to Non-Preemptive Real-Time Scheduling,” Real Time Systems 6(1):7-35 (1994).
Zaino et al., “Algorithm Analysis and Mapping Environment for Adaptive Computing Systems,” Final Technical Report, DARPA Contract F33615-97-C-1174 (Sep. 2001).
Zhang et al., “A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications,” 2000 IEEE Solid.
Abnous, Arthur et al., “Ultra-Low-Power Domain-Specific Multimedia Processors”; 1996, Workshop on VLSI Signal Processing, pp. 461-470.
Altera Apex 20K 1999.
Andraka Consulting Group, “Distributed Arithmetic,” Obtained from: http://www.fpga-guru.com/distribu.htm (1998-2000).
Bapty, T. et al., “Uniform Execution Environment for Dynamic Reconfiguration”; 1999, Darpa Adaptive Computing Systems, http://isis.vanderbilt.edu/publications/archive/Babty—t—3—0—1999 Uniform—Ex.—PDF, pp. 1-17.
Compton, Katherine et al., “Configuration Relocation and Defragmentation for Run-Time Reconfigurable Computing”; 2000, Northwestern University, http:/ /citeseer.nj.nec.com/compton00configuration.html, pp. 1-17.
Dehon, Andre et al., “Reconfigurable Computing. What, Why, and Implications for Design Automation”, 1999, Design Automation Conference Proceedings, pp. 610-615.
Hanna et al., “A Normalized Backpropagation Learning Algorithm for Multilayer Feed-Forward Neural Adaptive Filters,” Neural Networks for Signal Processing XI, Proceedings of the 2001 IEEE Signal Processing Society Workshop pp. 63-72 (Sep. 2001).
Janweijer et al., “A Compact Robin Using the SI Iarc (CRUSI I),” Obtained from: http://www.nikhef.nl/˜peterj/Crush/CRUSH-hw.pdf (Sep. 1998).
Rajagopalan et al., “A Flexible Multiplication Unit for an FPGA Logic Block,” Circuits and Systems 4:546-9 (2001).
Xilinx Data Book 1998.
Xilinx Virtex 1.1 1998.
Xilinx Virtex 2.2 2000.
Related Publications (1)
Number Date Country
20150261723 A1 Sep 2015 US
Continuations (3)
Number Date Country
Parent 14082691 Nov 2013 US
Child 14714993 US
Parent 12785868 May 2010 US
Child 14082691 US
Parent 10015530 Dec 2001 US
Child 12785868 US
Continuation in Parts (1)
Number Date Country
Parent 09815122 Mar 2001 US
Child 10015530 US