This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-122540, filed on Apr. 26, 2006; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of a manufacturing semiconductor device and manufacturing system and, more particularly, to a control of a semiconductor device manufacturing process.
2. Related Art
In a conventional semiconductor device manufacturing method, the yield thereof has been increased by improving uniformity of a surface of a wafer in each manufacturing process. Recently, as the semiconductor device is miniaturized and a size of the wafer is increased, it is difficult to improve the uniformity of the surface of the wafer in each manufacturing processes. Therefore, there is a limitation to the increasing of the yield through the improving of the uniformity of the surface of the wafer.
In order to solve the aforementioned problem, Japanese Patent Application Laid-Open No. 7-302826 (Patent Document 1) describes a product manufacturing method capable of increasing the yield by optimizing an uncompleted process according to a simulation result of the uncompleted process that is obtained by simulating a result of the uncompleted process based on a result of a completed process.
In addition, Japanese Patent Publication No. 6-16475 (Patent Document 2) describes an electronic circuit device manufacturing method of simulating a result of an uncompleted process based on a measurement result and history information of a completed process and selecting an optimal process according to a simulation result.
However, in the Patent Documents 1 and 2, a surface topography of the wafer cannot be considered. Therefore, in a case where a finished state tendency in a surface of a wafer (hereinafter simply described as in-surface tendency) is different among the processes, the yield in terms of the entire surface of the wafer cannot be increased.
According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method, comprising: measuring a finished state of a wafer in a completed process; estimating an in-surface tendency of the wafer based on a result of the measuring; estimating a surface characteristic of the wafer based on the estimated in-surface tendency; setting a process condition of a uncompleted process based on the estimated surface characteristic; and controlling the uncompleted process based on the set process condition.
According to a second aspect of the present invention, there is provided a semiconductor device manufacturing system comprising: an in-surface tendency estimation unit which measures a finished state of a wafer in a completed process and estimates an in-surface tendency of the wafer based on a result of the measuring; a characteristic estimation unit which estimates a surface characteristic of the wafer based on the estimated in-surface tendency; a process condition setting unit which sets a process condition of a uncompleted process based on the estimated surface characteristic; and a controller which controls the uncompleted process based on the set process condition.
Hereinafter, embodiments of the present invention are described with reference to the accompanying drawings. In the embodiments, methods and systems for implementing a technical spirit of the present invention are described. Therefore, the present invention is not limited to the embodiments described below.
The semiconductor device manufacturing system includes a controller 101, an in-surface tendency estimation unit 102, a characteristic estimation unit 103, a process condition setting unit 104, a partitioned data acquisition unit 105, a selection unit 106, a film forming process unit 107, a chemical mechanical polishing (CMP) process unit 108, an etching process unit 109, a storage unit 110, a pre-processing unit 111, and a post-processing unit 112. However, the components of the manufacturing system according to the present invention are not limited to the aforementioned components.
The storage unit 110 includes; a process condition storage part 110-1 which stores process conditions (process-unit parameters) used for process units; an in-surface tendency data storage part 110-2 which stores a estimation result obtained by the in-surface tendency estimation unit 102; a characteristic data storage part 110-3 which stores a estimation result obtained by the characteristic estimation unit 103; and a selection condition storage part 110-4 which stores a selection condition used for a selection operation. In addition, the storage unit 110 may store other data, for example, a control program for controlling the process units.
Firstly, the pre-processing unit 111 performs a pre-processing S201 including a process of cleaning a silicon wafer. Next, film forming process unit 107 performs a film forming process S202 to form a silicon nitride film (SiN film). Next, the controller 101 performs optimization S203 for the process conditions after the CMP process. Next, the CMP process unit 108 performs a CMP process S204 based on the optimized process conditions to polish the wafer. Next, the controller 101 performs optimization S205 for the process conditions after the etching process. Next, the etching process unit 109 performs an etching process S206 based on the optimized process conditions to form elements. Next, the controller 101 performs optimization S207 for the process conditions of the post-processing. Next, the post-processing unit 112 performs a post-processing S208 including a resist removing process based on the optimized process condition. When the manufacturing processes including the aforementioned processes are completed, the semiconductor device is formed on surface of the wafer.
The controller 101 controls the process units including the pre-processing unit 111, the film forming process unit 107, the CMP process unit 108, the etching process unit 109, and the post-processing unit 112 based on the process conditions stored in the process condition storage part 110-1. The process units perform the corresponding processes under the control of the controller 101.
A gate insulating film 302 and a polysilicon layer 303 are formed on a silicon (Si) substrate 301. Subsequently, a silicon nitride film (SiN film) 304 is deposited by using a chemical vapor deposition (CVD) method, and trenches are formed by using a photolithography method and an etching method. Here, a thickness TSiN of the SiN film 304 is selected as a finished data of the film forming process S202.
As shown in
As shown in
Although the processes S201 to S208 are described in the following embodiments, various other sequences of processes may be similarly performed. In the following embodiments, the processes S201 to S204 are assumed to be complete processes, and the processes S205 to S208 are assumed to be uncompleted processes.
Now, a semiconductor device manufacturing method and system according to a first embodiment of the present invention are described.
Firstly, in the in-surface tendency estimation unit 102, a finished data TSiN (see
Next, the in-surface tendency data (see
Next, it is determined whether or not the estimated electrical characteristic stratifies a specification over the entire surface of the wafer (in-spec). If the estimated electrical characteristic is determined not to be in the in-spec state (that is, in the out-of-spec state) (No in S706), the process condition setting unit 104 repeats the process condition setting (S704) until the electrical characteristic satisfies predetermined specification (it is in the in-spec state) over the entire surface of the wafer. If the estimated electrical characteristic is determined to be in the in-spec state (Yes in S706), the optimization is ended, and the set process condition is stored in the process condition storage part 110-1. Subsequently, the next process, that is, the etching process (S206) is performed.
As an example of the standard for determining the in-spec state, the following condition expressed by Equation 1 can be used. Here, E, T, and U denote the estimation result (an estimated value of electrical characteristic) of the characteristic estimation unit 103, a target value, and an allowable specification range (an allowable value).
T−U≦E≦T+U [Equation 1]
Namely, the controller 101 controls the process condition setting unit 104 so that the estimated value E of electrical characteristic E can be close to the target value T (or be in the range of the allowable value U). When the estimated value E of electrical characteristic E is close to the target value T, the entire surface of the wafer can be determined to be in the in-spec state (Yes in S706). Accordingly, the yield in term of the entire surface of the wafer can be increased.
Although the first embodiment is applied to the optimization S205 performed before the etching process, it can be applied to the optimization S203 performed before the CMP process and the optimization S207 performed after the etching process.
In addition, in the determination S706 of the in-spec state, the best-yield process condition may be selected and set among a plurality of process conditions (for example, the process condition of the film forming process, the process condition of the CMP process, and the process condition of the etching process) and combinations of the process conditions. In addition, in the setting S704 of the process condition, the process conditions of the completed processes, that is, the film forming process S202 and the CMP process S204 may be set, so that the yield of a new lot manufacturing process can be increased.
According to the semiconductor device manufacturing method and system of the first embodiment, the process condition of the uncompleted process is set based on the in-surface tendency of the wafer, so that the yield in terms of the entire surface of the wafer can be increased.
Now, a second embodiment of a semiconductor device manufacturing method and system of capable of further increasing the yield in comparison with the first embodiment is described. In description of the second embodiment, the same construction and operations as the first embodiment are omitted.
Firstly, in the partitioned data acquisition unit 105, partitioned data of predetermined partitioned regions (for example, meshes of a mesh shape shown in
Now, an example of the particle risk estimation operations (S902-1 and S902-2) are described with reference to
Referring to
In the second embodiment, the determination S906 of the in-spec state may be performed in the same manner as the determination S706 of the first embodiment. In addition, the in-surface tendency data and the particle risk stored in the in-surface tendency data storage part 110-3 may be used. For example, in a case where the electrical characteristic stored in the characteristic data storage part 110-3 is reflected on the particle risk stored in the in-surface tendency data storage part 110-3, if the yield become more than a predetermined value, it may be determined to be in the in-spec state. In addition, in the determination S906 of the in-spec state, the best-yield process condition may be selected and set among a plurality of process conditions (for example, the process condition of the film forming process, the process condition of the CMP process, and the process condition of the etching process) and combinations of the process conditions.
According to the semiconductor device manufacturing method and system of the second embodiment, the process condition is set by using the in-surface tendency data for each predetermined region, so that the yield in terms of the entire surface of the wafer can be further increased in comparison with the first embodiment. In addition, according to the embodiment, the particle risk is considered, so that the yield can be further increased.
Now, a third embodiment of a semiconductor device manufacturing method and system of capable of further Increasing a profit in terms of cost and performance in comparison with the second embodiment is described. In description of the third embodiment, the same constructions and operations as the first and second embodiments are omitted.
The selection unit 106 determines whether or not the performing of the uncompleted process (that is, the etching process S206 and the post-processing S208) is profitable by using the optimized process condition for the case of the in-spec state (Yes in S906) (S1303). If the performing of the uncompleted process is determined to be profitable (Yes in S1303), the next process, that is, the etching process S206 is performed. If the performing of the uncompleted process is determined not to be profitable (No in S1303), the etching process is not performed, but a new lot wafer manufacturing process is started (S201). Namely, the selection unit 106 selects the more profitable case between the case where the uncompleted process is performed (Yes in S1303) and the case where the new lot wafer is manufactured (No in S1303). In addition, when the new lot wafer is manufactured, the existing lot wafer where the performing of the CMP process is completed is discarded.
Now, an example of the determination S1303 of the selection unit 106 is described. The selection condition storage part 110-4 stores a sales data X associated with the yield obtained by the optimization, a sales data A associated with a standard yield, a cost data B1 associated with the performing of the manufacturing process shown in
X<A−B1 [Equation 2]
According to the semiconductor device manufacturing method and system of the third embodiment, if a wafer with the increased yield is determined not to be profitable, the etching process is not performed but a new lot wafer is manufactured, so that a loss caused from the manufacturing of an unnecessary lot wafer can be prevented. This can be easily seen from the verification result shown in
The processes shown in
Number | Date | Country | Kind |
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2006-122540 | Apr 2006 | JP | national |