METHOD AND SYSTEM FOR VERIFYING THE EQUIVALENCE OF DIGITAL CIRCUITS

Abstract

The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention and its advantages are now described in conjunction with the accompanying drawings.

FIG. 1 is a schematic block diagram illustrating two designs in accordance to be checked for equivalency;

FIG. 2 is a flow chart describing a preferred embodiment of the present invention;

FIG. 3 is a timing diagram applicable to the values of logical signals;

FIG. 4 is a flow chart of another embodiment of the present invention;

FIG. 5 is a schematic block diagram of latches; and

FIG. 6 is a schematic block diagram of a wrapper in accordance with the invention.

Claims

1. A method for verifying equivalent digital circuits (10) by comparing values of selected outputs (16, 17) for equal values of selected inputs (12, 13) thereof, the method comprising the steps of: a) analyzing (1) global clock configurations of said selected inputs and said selected outputs;b) equalizing said global clock configurations by modifying (2) design representations of said digital circuits (Code A, Code B); andc) determining the equivalency of said digital circuits (10) by comparing (3) the modified design representations (Wrapper A, Wrapper B).

2. The method of claim 1, wherein in step a), said global clock configurations are determined by analysing (4, 5, 6) the clock configurations of respective relevant storage elements, wherein said relevant storage elements are modified by said selected inputs or modify said selected outputs.

3. The method of claim 2, wherein in step b), said global clock configurations are equalized (7) based on said relevant storage elements of said clock configurations.

4. The method of claim 3, wherein in step b), said equalization results in an equivalent offset to timing axes of said selected inputs and selected outputs.

5. The method of claim 3, wherein in step b), added logic elements (20, 21) are inserted in said design representations and are connected to inputs or outputs that are not part of said selected inputs or outputs.

6. The method of claim 3, wherein in step b), added storage elements (18, 19) are inserted (8) in said design representations and are connected to a subset of said selected inputs and said selected outputs.

7. The method of claim 6, wherein inputs and outputs (16, 17) of said additional storage elements are used in step c).

8. The method of claim 7, wherein step c) is performed using a functional formal verification tool.

9. The method of claim 8, wherein said design representations are specified in hardware description languages, and wherein the analysing step is performed in a lexical analysis tool.

10. The method of claim 9, wherein said lexical analysis tool is based on coding conventions.

11. The method of claim 8, wherein said design representations are RTL or a gate-level netlist representation of the logic design.

12. The method of claim 5, wherein the additional logic elements (20, 21) inserted in said design representations are connected to inputs or outputs that are not part of said selected inputs or outputs

13. The method of claim 12, wherein said inputs are selected from a group consisting of clock and clock control signals, scan-path and scan-path control signals, and reset signals.

14. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for verifying equivalent digital circuits (10) by comparing values of selected outputs (16, 17) for equal values of selected inputs (12, 13) thereof, the method comprising the steps of: analyzing (1) global clock configurations of said selected inputs and said selected outputs;equalizing said global clock configurations by modifying (2) design representations of said digital circuits (Code A, Code B); anddetermining the equivalency of said digital circuits (10) by comparing (3) the modified design representations (Wrapper A, Wrapper B).

15. The program storage device of claim 14, wherein the comparing step is performed by a tool selected from a group consisting of a checker, a SAT checker, a semiformal verification tool, a simulation tool, and any combination thereof.

16. A computer program product comprising: a computer usable medium having computer readable program code means embodied therein for verifying equivalent digital circuits (10) by comparing values of selected outputs (16, 17) for equal values of selected inputs (12, 13) thereof, the computer readable program code means in said computer program product comprising:computer readable program code means for causing a computer to analyze (1) global clock configurations of said selected inputs and said selected outputs;computer readable program code means for causing the computer to equalize said global clock configurations by modifying (2) design representations of said digital circuits (Code A, Code B) coupled to said computer readable program code means for causing the computer to analyze (1) global clock configurations; andcomputer readable program code means for causing the computer to determine the equivalency of said digital circuits (10) by comparing (3) the modified design representations (Wrapper A, Wrapper B), coupled to said computer readable program code means for causing the computer to equalize said global clock configurations by modifying (2) design representations of said digital circuits.