Dean M. Tullsen, et al., “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor” Dept. of Computer Science & Engineering, University of WA, Seattle, WA. |
Roa P. Pokala, et al., “Physical Synthesis for Performance Optimization”, Vertex Semiconductor, San Jose, CA. |
Gregory T. Byrd, et al., “Multithreaded Processor Architectures”, Western Carolina University, 8045 IEEE Spectrum, 32 (1995) Aug., No. 8, New York, U.S. |
Mark R. Thistle, et al., “A Processor Architecture For Horizon”, Institute for Defense Analyses, Supercomputing Research Center, Lanham, Maryland 20706. |
Steere D, et al., “A Feedback-driven Proportion Allocator for Real-Rate Scheduling”, Third Symposium on Operating Systems Design and Implementations, Feb. 22-25, 1999, pp. 145-158, XP002153159. |
Intel, “P6 Family of Processors”, Hardware Developer's Manual, Sep. 1998, XP-002153160. |
IBM, “Improved Dispatching in a Rendering Context Manager”, IBM Technical Disclosure Bulletin, Dec. 1990, pp. 131-134, vol. 33, No. 7, XP000108363 ISSN: 0018-18689, Armonk, NY. |
Farrens, MK; Pleszkun, AR., “Strategies for Archieving Improved Processor Throughout”, The 18th Annual International Symposium on Computer Architecture, May 27-30, 1991, pp. 362-369. |
Mendelson, A; Berkerman, M., “Design Alternatives of Multithreaded Architecture”, International Journal of Parallel Programming, Dec. 9, 1996, vol. 27, No. 3, pp. 161-193, Pullenum Publishing Corporation. |
James Laudon, Anoop Gupta and Mark Horowitz, “Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors”, Multithreaded Computer Architecture: A Summary of the State of the Art, Chap. 8, pp. 167-200, Kluwer Academic Publishers 1994. |
Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo and Rebecca L. Stammm, “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor”, Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 22-24, 1996, pp. 191-202. |
Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante and Shiafun Liu, “Evaluation of Multithreaded Uniprocessors for Commercial Application Environments”, Proceedings of the 23rd Annual International Symposium on Computer Architecture. May 22-24, 1996, pp. 203-212. |
Manu Gulati and Nader Bagherzadeh, “Performance Study of a Multithreaded Superscalar Microprocessor”, Proceedings Second International Symposium on High-Performance Computer Architecture, Feb. 3-7, 1996, pp. 291-301. |
R. Guru Prasadh and Chuan-Lin Wu,“A Benchmark Evaluation of a Multi-Threaded RISC Processor Architecture”, 1991 International Conference on Parallel Processing, pp. I-84-I91. |
Peter Song, “Multithreading Comes of Age”, Microdesign Resources, Jul. 14, 1997, pp. 13-18. |
Dennis Lee, Jean-Loup Baer, Brad Calder and Dirk Grunwald, “Instruction Cache Fetch Policies for Speculative Execution”, 22nd International Symposium on Computer Architecture, Jun. 1995. |
Ruediger R. Asche, “Multithreading for Rookies”, Http://www.microsoft.com/win32dev/base/threads.htm, Jul. 31, 1998. |
Simon W. Moore, “Multithreaded Processor Design”, Kluwer Academic Publishers, 1996. |
Dongwook K., et al., “A Partitioned On-Chip Virtual Cache for Fast Processors”, Journal of Systems Architecture, Elsevier Science Publishers BV., Amsterdam, NL, vol. 43, No. 8, May 1, 1997 (1997-05-01), pp. 519-531, XP000685730. |
International Search Report-PCT/US00/10800-Feb. 20, 2001. |
Rosenberg Dictionary of Computers, Information Processing and Telecommunications, pp. 299-300, 1987. |