Claims
- 1-79. (Cancelled)
- 80. A memory device, for use with a semiconductor processing apparatus that performs at least one wafer processing step for each batch of one or more provided wafers, the memory device comprising instructions for the apparatus to perform a method comprising:
determining, in accordance with at least one of a detected condition of the apparatus and a command received from a computer coupled to the apparatus, that a provided batch over which the apparatus has control is not to participate in the wafer processing step; and in response to a result of determining, inhibiting participation of the batch in the wafer processing step without interfering with wafer processing currently being applied to a second wafer not in the batch.
- 81. The memory device of claim 80 wherein determining comprises detecting an alarm condition.
- 82. The memory device of claim 80 wherein determining comprises evaluating a user-defined condition of process parameters.
- 83. The memory device of claim 80 wherein determining is in accordance with at least one of a detected condition of the apparatus, a command received from a computer coupled to the apparatus, and a condition of a third wafer, the apparatus having already applied the wafer processing step to the third wafer.
- 84. The memory device of claim 80 further comprising performing a recovery procedure on the batch.
- 85. The memory device of claim 84 wherein:
determining is repeated to provide an updated result prior to inhibiting; and inhibiting is performed after lapse of a predetermined time and in accordance with the updated result.
- 86. A semiconductor processing apparatus comprising the memory of any of claims 80 through 85.
- 87. A memory device for use with a semiconductor processing apparatus that includes a first wafer processing step followed by a second wafer processing step for each batch of one or more provided wafers, the memory device comprising instructions for the apparatus to perform a method comprising:
determining, in accordance with at least one of a detected condition of the apparatus and a command received from a computer coupled to the apparatus, that a provided batch over which the apparatus has control is not to participate in the second step of wafer processing; in response to a result of determining, inhibiting participation of the batch in the second step of wafer processing; and performing a recovery procedure on the batch so that the batch does not interfere with operation of the first step of wafer processing on a provided subsequent batch.
- 88. A semiconductor processing apparatus comprising the memory of claim 87.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional application of and claims priority to U.S. patent application Ser. No. 10/071,761, filed Feb. 6, 2002 by Komelius Haanstra, Marinus Jan Van Der Pol, and Jan Zinger.
Divisions (1)
|
Number |
Date |
Country |
Parent |
10071761 |
Feb 2002 |
US |
Child |
10838510 |
May 2004 |
US |