A Serial Peripheral Interface bus is a synchronous serial data link standard that generally operates in a full duplex mode. Devices generally communicate in a master/slave mode where the master device initiates the data frame. Multiple slave devices can be manipulated with a singular Master device. Multiple devices are allowed to have slave select lines. An SPI can be a four-wire serial bus. If a single slave device is used, an SS pin can be fixed to a logic that selects the single slave. Some slaves require a falling edge (high to low transition) of the chip select to initiate an action. To begin a communication, the bus master will first configure the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1 to 100 MHz, for example. Flash memories compatible to Serial Peripheral Interface (SPI) bus protocol use the falling clock edge for launching data and the rising clock edge for capturing data. Flash memories are often interfaced with an on-chip device and it is often not possible to operate the memories at highest device frequency due to memory clock to Q, chip pad delay and combinational logic inside the chip. In conventional methods, the memory operates at lower frequency based on the read data path delays and not at a device rated frequency.
An embodiment of the invention may therefore comprise a system for capturing data when a flash memory is interfaced with on-chip devices, the system comprising a flash memory with a read-data output and an on-chip capture register, wherein the memory operates on a master clock and the capture register operates on a peripheral clock, the peripheral clock operating at a higher frequency than the master clock and synchronous to said master clock, and read data is captured by the capture register on a cycle of the peripheral clock when the master clock is high and read data is available at the capture register.
An embodiment of the invention may further comprise a method of capturing data when a flash memory is interfaces with on-chip devices, the method comprising operating the memory with a master clock, operating a capture register located on-chip with a peripheral clock and capturing read data by capture register on a cycle of the peripheral clock when the master clock is high and read data is available at the capture register, wherein the peripheral clock is synchronous with the master clock and operates at a higher frequency than the master clock.
a shows a hardware setup using two shift registers to form an inter-chip circular buffer.
b is a timing diagram for an SPI.
a shows a hardware setup using two shift registers to form an inter-chip circular buffer, as an example of an SPI master/slave configuration. To begin a communication, the bus master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. During each SPI clock cycle, a full duplex data transmission will occur. This means that the master 110 will send a bit on the MOSI line 115—and the slave 120 will read it from that same line. The slave will send a bit on the MISO line 125 and the master will read if from that same line. It is understood that not all transmissions require all four of these operations.
Transmissions may involve two shift registers 130 of some given word size, such as 8 bits. One register 130 is in the master 110 and one register is in the slave 120. Transmissions may involve any number of clock cycles. When data has completed transmission, the master 110 will stop toggling its clock.
The master 110 will set a clock frequency and configure a clock polarity and phase with respect to the data. CPOL and CPHA are respectively the conventional names used for these two options.
The master determines an appropriate CPOL and CPHA value. The master pulls down the slave select (SS) line for a specific slave chip. The master clocks SCK at a specific frequency. During each of the 8 clock cycles 260, the transfer is full duplex. This means the master writes on the MOSI line and reads the MISO line during each cycle. The slave writes on the MISO and reads the MOSI line each cycle.
Memory data is captured correctly when the period of A is greater to that of the period of B+the period of C. This leads to reduced memory operating frequency and an increased boot loader down load time.
The capture register 420 operates on the peripheral clock PCLK 425 and the memory 400 operates on the master clock MCLK 410. The peripheral clock PCLK 425 operates at a higher frequency than the master clock MCLK 410. The peripheral clock PCLK and the master clock MCLK are both synchronous to each other.
The memory read data is captured by the peripheral clock PCLK 510 rather than by the master clock MCLK 520. As PCLK 510 operates at a higher frequency, memory read data path can be captured at multiple rising edges of PCLK 510 during MCLK 520 high times. This can be based on the read data availability at the capture register D 530. In the waveform, PCLK cycle cy3514 is the first available period to capture read data at the capture register input D 530 The memory can be operated at a rated frequency successfully even if the read data path delay is higher than the memory half clock period. The configure register 440 of
The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.