Patent Application
20080270100
The present invention relates generally to the semiconductor devices, and more particularly to a method, apparatus and computer program product for implementing optimized channel routing with automated generation of finite impulse response (FIR) driver and receiver coefficients for compensation in an electronic package design.
In today's physical design environment, printed circuit boards typically are routed based on a set of constraints that are inputted into a design file. These constraints are used to govern the physical layout of the nets based on length, number of vias, available layers, spacing, and the like.
The constraints are usually generated based on simulation results and are used to ensure the wiring constructs of the resulting PCB design are representative of the wiring constructs that were simulated. This requires an electrical to physical translation of the transmission line characteristics. This approach requires considerable up front work to accurately model and simulate the multiple possible physical layout configurations. The performance limiting physical layouts are then translated to physical constraints and are inputted into the physical design constraint management system.
U.S. Pat. No. 6,975,140 to Louis L. Hsu et al, issued Dec. 13, 2005 and assigned to the present assignee, discloses a data transmitter and transmitting method in which an adaptive finite impulse response (FIR) driver has a plurality of taps to which coefficients having updateable values are applied. The FIR driver has a transfer function between an input stream of data bits and an output stream of data bits such that each data bit output from the FIR driver has an amplitude adjusted as a function of the values of a plurality of data bits of the input stream, and the values of the coefficients. The data transmitter includes a rewriteable non-volatile storage, operable to be rewritten with control information representing the values of the coefficients updated during operation of the FIR driver.
A need exists for an effective mechanism for optimized channel routing with automated generation of finite impulse response (FIR) driver coefficients for compensation in an electronic package design.
As used in the following description and claims, the term net means a connection or wire between a number of integrated circuit chips or between transistors in a circuit.
As used in the following description and claims, the term FIR driver coefficients should be understood to include either finite impulse response (FIR) driver coefficients or FIR receiver coefficients, or a combination of FIR driver coefficients and FIR receiver coefficients.
Principal aspects of the present invention are to provide a method, apparatus and computer program product for implementing optimized channel routing with automated generation of finite impulse response (FIR) driver coefficients for compensation in an electronic package design. Other important aspects of the present invention are to provide such method, apparatus and computer program product for implementing optimized channel routing in an electronic package design substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method, apparatus and computer program product are provided for implementing optimized channel routing in an electronic package design. Electronic package physical design data are received. A physical design including a netlist including a plurality of nets is generated. Initial FIR driver coefficients are determined for each net in the netlist from simulation with generation of impulse responses of the netlist.
In accordance with features of the invention, when required performance is not met, the I/O circuit model is updated with compensation based upon updated coefficients. Then re-simulation of the netlist is provided for a re-evaluation of the FIR driver to provide updated coefficients. This adjustment loop can be repeated until required performance criteria are achieved. Identified FIR coefficients are provided for the routed channel nets in the physical design. Additionally the optimal FIR coefficients for a given routed channel net are generated.
In accordance with features of the invention, a table of FIR coefficients is used with a matching signal name for each net in the netlist for identified FIR driver coefficients.
The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
In accordance with features of the invention, design system methods are provided for implementing optimized channel routing with automated generation of finite impulse response (FIR) driver coefficients for compensation in an electronic package design. The FIR driver coefficients are identified and are provided with each routed channel net in the physical design. The FIR driver coefficients are chosen for each net in a netlist based upon a simulation after physical design including the netlist. No memory is required for storing FIR driver coefficients, as used in prior art arrangements.
Referring now to the drawings, in
Computer system 100 is shown in simplified form sufficient for understanding the present invention. The illustrated computer system 100 is not intended to imply architectural or functional limitations. The present invention can be used with various hardware implementations and systems and various other internal hardware devices, for example, multiple main processors.
As shown in
Various commercially available computers can be used for computer system 100, for example, an IBM personal computer. CPU 102 is suitably programmed by the FIR coefficient control program 134 to execute the flowchart of
Referring to
Referring now to
Electronic and package physical design data and design inputs for an electronic package design are received as indicated a block 302 including a PCB model suite, and a block 304 including interconnect feature models, for example, vias, connectors.
Optionally vendor provided I/O circuit models as indicated at a block 306, and package model suite as indicated at a block 308 are received and applied to a map of signal names to I/O cell and package model as indicated in a block 310.
An analysis tool used to generate a netlist as indicated at a block 312 receives a wiring topology definition as indicated at a block 314 and is coupled to the PCB model suite block 302, interconnect feature models block 304, and the map of signal names to I/O cell and package model block 310.
The appropriate PCB model is selected at block 302 based on the cross-section and line-width used and added to the netlist along with the wire length at block 312. An interconnect feature, such as a via or connector, at block 304 is also added to the netlist at block 312. Also by using the associated signal name at block 310, the mapped I/O cell and package model are also added to the netlist at block 312.
An initial netlist as indicated at a block 316 is provided by the generate netlist tool block 312. The initial netlist at block 316 is created for each net and signal as transmission lines and features are added during board routing. The initial netlist at block 316 includes a circuit description of the signal topology with I/O models.
Simulation of the netlist is performed as indicated at a block 322, with generation of impulse responses of the netlist as indicated at a block 324. A table of FIR coefficients is determined for the simulation output including, for example, FIR coefficient values used in determining effective levels of driver and/or receiver compensation for a certain I/O circuit model and signal net topology as indicated at a block 325. Then the identified FIR coefficients are used in testing against predefined performance criteria as indicated at a block 326. As indicated at a decision block 328, it is determined whether the identified FIR coefficients pass the test. If the selected FIR coefficients pass testing against the predefined performance criteria, then the FIR coefficients are selected as indicated at a block 330.
If the identified FIR coefficients do not pass testing against the predefined performance criteria, then updated circuit I/O models with updated FIR coefficients are provided as indicated at a block 332. A netlist is created with the modified I/O circuit models including the updated FIR coefficients as indicated at a block 334. Then simulation of the new netlist is performed at block 322, analysis of the netlist with generation of impulse responses of the netlist is performed at block 324, and the table of FIR coefficients is determined for the simulation output at block 325. Testing is performed to determine if the required performance criteria is met with the updated FIR coefficients. If so, then the updated FIR coefficients are selected at block 330. Otherwise, the adjustment loop is repeated.
Referring now to
Electronic and package physical design data and design inputs for an electronic package design are received as indicated a block 402 including a PCB model suite, and a block 404 including interconnect feature models, for example, vias, connectors.
Optionally vendor provided or other available I/O circuit models as indicated at a block 406, and package model suite as indicated at a block 408 are received and applied to a map of signal names to I/O cell and package model as indicated in a block 410.
An analysis tool used to generate a netlist as indicated at a block 412 receives a wiring topology definition as indicated at a block 414 and is coupled to the PCB model suite block 402, interconnect feature models block 404, and the map of signal names to I/O cell and package model block 410.
An appropriate PCB model is selected at block 402 based on the cross-section and line-width used and added to the netlist along with the wire length at block 412. An interconnect feature, such as a via or connector, at block 404 is also added to the netlist at block 412. Also by using the associated signal name at block 410, the mapped I/O cell and package model are also added to the netlist at block 412.
An initial netlist as indicated at a block 416 is provided by the generate netlist tool block 412. The initial netlist at block 416 is created for each signal as transmission lines and features that are added during board routing and includes a circuit description of the signal topology. Simulation of the netlist is performed as indicated at a block 422, and analysis with generation of impulse responses of the netlist is performed as indicated at a block 424. Initial FIR coefficient values are created for the simulation output including, for example, FIR coefficient values used in determining effective levels of driver compensation for a certain I/O and topology as indicated at a block 425. Then the identified FIR coefficients are used in testing against predefined performance criteria as indicated at a block 426. As indicated at a decision block 428, it is determined whether the identified FIR coefficients pass the test. If the selected FIR coefficients pass testing against the predefined performance criteria, then the FIR coefficients are selected as indicated at a block 430.
If the identified FIR coefficients do not pass testing against the predefined performance criteria, then feedback optionally is provided to a designer as indicated at a block 432. Next updated I/O models with FIR coefficients are provided, optionally utilizing input from the designer, as indicated at a block 434. A netlist is created with the modified I/O circuit models as indicated at a block 436. Then re-simulation of the new netlist and analysis of the netlist using an impulse response is performed as indicated at a block 438, then updating to create improved FIR coefficients is provided as indicated at a block 440. Testing is performed again to determine if the required performance criteria is met with the updated FIR coefficients at block 426. If so, then the updated FIR coefficients are selected at block 430. Otherwise, the adjustment loop is repeated.
Referring to
Referring now to
A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means 604, 606, 608, 610, direct the computer system 100 for implementing optimized channel routing with automated generation of finite impulse response (FIR) driver coefficients of the preferred embodiment.
While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
