The present invention relates generally to the data processing field, and more particularly, relates to a method, apparatus and computer program product for implementing polymorphic reconfiguration of a cache size.
Computers have become increasingly faster and one of the ways in which to increase the speed of computers is to increase the clock speed of the processors. Computer system performance is limited by processor stalls when the processor must wait for data from memory to continue processing. In order to reduce data access time, special purpose high-speed memory spaces of static random access memory (RAM) called a cache are used to temporarily store data which are currently in use. For example, the cached data can include a copy of instructions and/or data obtained from main storage for quick access by a processor.
A processor cache typically is positioned near or integral with the processor. Data stored in the cache advantageously may be accessed by the processor in only one processor cycle retrieving the data necessary to continue processing; rather than having to stall and wait for the retrieval of data from a secondary memory, such as a higher level cache memory or main memory.
Since cache size directly impacts cache latency, processor designs must decide between a smaller cache with shorter latency, or a bigger cache with a longer latency.
Various computer applications require varying amounts of cache to run well. Since many processors are designed to run well over a wide range of applications, caches are often sized for larger applications.
Since larger caches result in longer access times, applications that can perform well in a smaller cache needlessly suffer from the longer access times imposed by the demands of other workloads.
Principal aspects of the present invention are to provide a method, apparatus and computer program product for implementing polymorphic reconfiguration of a cache size. Other important aspects of the present invention are to provide such method, apparatus and computer program product for implementing polymorphic reconfiguration of a cache size substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method, apparatus and computer program product are provided for implementing polymorphic reconfiguration of a cache size. A cache includes a plurality of physical sub-banks. A first cache configuration is provided. Checking is provided to identify improved performance with another cache configuration. The cache size is reconfigured to provide improved performance based upon the current workload.
In accordance with features of the invention, in a small cache size configuration, a physical sub-bank of the cache closest to user logic is used. A wire delay for both sending a request to cache and for retrieving data from the cache is minimized when the closest physical sub-bank of the cache is used for the small cache size configuration.
In accordance with features of the invention, each physical sub-bank of the cache not being used in a small cache size configuration is powered down. Alternatively, one or more physical sub-banks of the cache not being used in a small cache size configuration can be used to store other information.
The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
In accordance with features of the preferred embodiment, the method for reconfiguring the cache size is adapted to match the needs of the workload. The cache is configured into a small/fast mode of operation for workloads that can fit in a small cache. For workloads that require the entire cache, the entire cache is used. The method for implementing polymorphic reconfiguration of cache size is performed using a cache physical sub-banking commonly used in cache arrays. The decision to switch cache size configurations can be made by software, and/or by adaptive hardware learning.
Having reference now to the drawings, in
Computer system 100 is shown in simplified form sufficient for understanding the present invention. The illustrated computer system 100 is not intended to imply architectural or functional limitations. The present invention can be used with various hardware implementations and systems and various other internal hardware devices, for example, multiple main processors, each used with at least one associated cache.
Referring to
A final output latch 210 is coupled via a multiplexer 208 to each out latch 206 associated with the respective sub-banks 202 # 1-4. A respective data #1-4 output bus connects each respective out latch 206 associated with the respective sub-banks 202 # 1-4 to the multiplexer 208. A bypass data #4 output bus directly connects the sub-bank 202 # 4 to the final output latch 210, bypassing the associated out latch 206.
For example as shown in
In a large cache size configuration, each of the plurality of sub-banks 202 # 1-4 is used. The large cache size configuration is provided for workloads or larger applications that require the entire cache.
In a small cache size configuration, the physical sub-bank 202 # 4 of the cache is used that is closest to user logic. A wire delay for both sending a request to cache and for retrieving data from the cache is minimized by using the closest physical sub-bank 202 # 4 for the small cache size configuration. The small cache size configuration is provided to improve system performance for other workloads or applications where the entire cache is not needed.
Referring to
If the small cache size configuration would not provide improved performance, then the large cache configuration is maintained at block 402. If small cache size configuration would provide improved performance, then the cache is reconfigured as indicated in a block 406. With the small cache configuration, such as using only sub-bank 202, # 4, the other sub-banks 202, # 1-3 optionally are powered down or used to store other information as indicated at block 406.
Checking current workload to identify improved performance with another cache configuration or the large cache size configuration is performed as indicated in a decision block 408. If the large cache size configuration would not provide improved performance, then the small cache configuration is maintained at block 406. If the large cache size configuration would provide improved performance, then the cache is reconfigured to the large cache configuration at block 402.
Cache controller 128 is arranged for implementing method polymorphic reconfiguration of cache size in accordance with the preferred embodiment, such as shown in
Referring now to
A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means 504, 506, 508, 510, direct the computer system 100 for implementing polymorphic reconfiguration of cache size of the preferred embodiment.
While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.