Patent Application
20220247621
The technology of the disclosure relates generally to distributed sensor monitoring on a system-on-chip (SoC), and specifically to the management and collection of data from a plurality of different types of sensors across an SoC.
In order to respond to various conditions and events that may occur across a system-on-chip (SoC), such as a microprocessor, the SoC may include a plurality of different types of sensors. These sensors collect and report information related to the operation of the SoC. This information may be used to respond to various conditions and events that occur during operation of the SoC. Examples of types of sensors that may be used include, but are not limited to, temperature sensors (which measure the temperature at a particular physical location on the SoC) and power event monitors (which observe and report on power events at a particular physical location on the SoC). The information collected by these sensors may allow other control circuits (such as a power management processor or similar) to make changes to the operating parameters of the SoC to mitigate problems related to the conditions and events that the sensors are capable of detecting.
In conventional implementations, an SoC includes a power or system management processor, which is responsible for collecting information from the various sensors that may be present on the SoC, evaluating the information from those sensors, and changing the operating parameters of the SoC accordingly. In such implementations, the management processor individually queries each sensor, and each sensor includes a buffer in which the sensor accumulates data while it waits to be queried by the management processor.
As the physical size of SoCs increases, thus increasing the total physical area across which sensors may be distributed, it is advantageous to concurrently increase the number of sensors. However, increasing the number of sensors may be problematic in conventional implementations, because as the number of sensors increases, the management processor may either spend a longer time interval between successive queries to each sensor (if the amount of data retrieved from each sensor remains constant, as more sensors must now be queried before returning), or the amount of data retrieved from each sensor may be reduced (in order to maintain the same time interval between queries to the same sensor). In either case, this may cause unacceptable degradation in the ability of the management processor to react to the events and conditions that the various sensors may detect, which in some cases may cause unrecoverable faults which necessitate a reboot of the SoC.
This may cause particular problems where the SoC is both relatively physically large (and thus may experience a significant variety of conditions and events across different parts of the physical die) and is operating in a cloud environment which depends on reliable uptime for such SoCs. In the case of such SoCs, the ability of a management processor to adjust to such events and conditions is relatively more important, but conventional implementations may be unable to either respond quickly enough to prevent unnecessary reboots, or may select unacceptably low performance parameters for the SoC to compensate for the lack of quick response. Thus, a system to manage and collect sensor data across a large physical chip that retains the ability to respond quickly to various conditions and events that may be detected by those sensors is desirable.
Aspects disclosed in the detailed description include a system for collecting and managing data from a plurality of sensors across an SoC, and related apparatus and method.
In this regard in one aspect, an apparatus comprises an external memory and a system management processor coupled to the external memory and configured to be programmed by the external memory. The apparatus further comprises a plurality of sensor circuits coupled to the system management processor and the external memory and configured to be programmed by the external memory. The external memory stores configuration information for programming each of the plurality of sensor circuits to collect and provide data concurrently with each of the others of the plurality of sensor circuits to be analyzed by a management firmware program and a management firmware program configured to analyze data received at the system management processor from the plurality of sensor circuits. The external memory is configured to program the system management processor and the plurality of sensor circuits.
In this regard, in another aspect, an apparatus comprises means for storing information and means for system management processing coupled to the means for storing information. The means for system management processing is configured to be programmed by the means for storing information. The apparatus further comprises a plurality of means for sensing coupled to the means for system management processing and the means for storing information, and configured to be programmed by the means for storing information. The means for storing information further stores configuration information for programing each of the plurality of means for sensing to collect and provide data concurrently with each of the others of the plurality of means for sensing to be analyzed by means for analyzing sensor data, and means for analyzing sensor data configured to analyze data from the plurality of means for sensing. The means for storing information is configured to program the means for system management processing and the means for sensing.
In this regard, in yet another aspect, a method comprises programming a plurality of sensors to collect and concurrently provide data, and programming a system management processor with management firmware configured to analyze data collected from the plurality of sensors. The method further comprises concurrently receiving data from the plurality of sensor circuits at the management processor, and determining a response by the management firmware based on analyzing the concurrently-received data.
In this regard, in yet another aspect, a non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause the processor to program a plurality of sensors to collect and concurrently provide data and program a system management processor with management firmware configured to analyze data collected from the plurality of sensors. The instructions further cause the processor to concurrently receive data from the plurality of sensor circuits by the management processor and determine a response by the management firmware based on analyzing the concurrently-received data.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include [to be completed after claims are approved].
In this regard,
In order to provide concurrent information from across the SoC 105, the power event monitors 102a-108a, 120a, and 132a-134a and the temperature sensor monitors 102b-108b, 120b, and 132b-134b (all of which together may be collectively referred to as the “SoC sensors”) may be programmable, and thereafter may concurrently communicate with the system management processor 120, either independently or in response to a single triggering event. The power event monitors 102a-108a, 120a, and 132a-134a, and the temperature sensor monitors 102b-108b, 120b, and 132b-134b may be configured to be programmed as part of a firmware programming by the external memory 190 of the SoC 105 (which may also include programming the management firmware program 125 of the system management processor 12) during power-on and boot time of the SoC 105, as part of a reset of the SoC 105, or at other times that may be determined by those having skill in the art.
As will be discussed in more detail with respect to
In one aspect, the management firmware program 125 may analyze data received from the power event monitors at a first time interval, and may analyze data received from the temperature sensor monitors at a second time interval. The first time interval and the second time interval may be the same, or may be different; in one aspect, the first time interval may be 100 microseconds, and the second time interval may be 10 milliseconds. In the context of the present disclosure, “concurrent” need not be simultaneous or substantially simultaneous, but rather may simply indicate that the data for the particular type of sensor can be updated within the associated time interval (i.e., for power event monitors, all of the power event monitors are able to communicate their data back to the management firmware program 125 over the system bus 110 within the first time interval of 100 microseconds, and for temperature sensor monitors, all of the temperature sensor monitors are able to communicate their data back to the management firmware program 125 over the system bus 110 within the second time interval of 10 milliseconds). As those having skill in the art will appreciate, the exact intervals are a matter of design choice, and may be chosen based on the size of the SoC 105, the number of sensors of both types, the complexity and speed of the interconnect over which the sensors communicate with the management firmware program 125, the desired speed of response of the management firmware program 125 to power or temperature events in the SoC 105, and others that may occur to those having skill in the art.
In the aspect depicted in
The data collected from all of the SoC sensors is stored in the sensor data buffer 120c, and the management firmware program 125 may evaluate the data in the sensor data buffer 120c and determine a response to events and conditions in the SoC 105 based on that data. Because the data in the sensor data buffer 120c was collected substantially concurrently (i.e., was updated within the associated time interval as described above) from all the SoC sensors across the entire physical area of the SoC 105, the management firmware program 125 may be able to determine a response that is relatively quicker and more targeted than would have been possible with a more conventional design. For example, the management firmware program 125 may evaluate temperature data from all of the temperature sensor monitors 102b-108b, 120b, and 132b-134b, and may determine that only the fourth processing core 108 is nearing a thermal limit (based on the data from temperature sensor monitor 108b). Thus, instead of lowering the frequency across the entire SoC 105, the management firmware program 125 may be able to lower the frequency of only the fourth processing core 108, while maintaining better performance across the rest of the SoC 105. Similarly, the management firmware program 125 may evaluate power data from all of the power event monitors 102a-108a, 120a, and 132a-134a, and may be able to determine that based on a sum of all the power data that the SoC 105 is approaching its maximum thermal design power (TDP) and that the second processing core 104 is the largest contributor. Based on this determination, the management firmware program 125 may take action to reduce the power consumption of the second processing core 104 while allowing the rest of the SoC 105 to operate normally. Further, the management firmware program 125 may report the data in the sensor data buffer 120c to an operating system or a hypervisor, which may take advantage by scheduling new processes on processing cores that are at relatively lower temperatures than other processing cores, as an example.
The sensor circuit 210 includes a bus interface 218 coupling the sensor circuit 210 to a system bus 110 as described above, and a programming interface 212 which is responsive to being programmed as described above, and which may be coupled to the system management processor via the system bus 110 (and alternatively through the bus interface 218) or may be coupled to the system management processor via a separate interface. The programming interface 212 is coupled to a timer 216 and a control block 214, and may provide an interface for programming either or both the timer 216 and the control block 214 by the system management processor 120. The control block 214 is coupled to and responsive to the timer 216, and couples to the sensor 220 and the bus interface 218. The control block 214 may allow the sensor circuit 210 to provide data back to the system management processor 120 by initiating a transaction on the system bus 110, either independently based on the programming of the timer 216, in response to a triggering event from the management firmware program 125 as described with respect to
In an aspect where the sensor 220 is a temperature, sensor, the programming interface 212 may program the timer 216 with a rate at which the control block 214 is to sample data from the sensor 220 and provide that data to the system management processor via the bus interface 218 and the system bus 110. The programming interface 212 may in some aspects further program the control block 214 with information such as a memory address of the system management processor to which data from the sensor 220 should be written, a specific temperature threshold that represents an “over temperature” condition (which may be provided as additional information back to the system management processor when the temperature value from the sensor 220 exceeds this threshold), and other related information. The information described above with which the sensor is programmed may be referred to as “configuration information.”
In an aspect where the sensor 220 is a power event sensor, the programming interface 212 may again program the timer 216 with a time period over which the control block 214 is to sample data from the sensor 220, and may program the control block 214 to provide data back to the system management processor 120 in response to a triggering event from the management firmware program 125. In some aspects, the programming interface 212 may additionally program the control block 214 with a memory address of the system management processor to which data from the sensor 220 should be written, and a number of samples over which to compute a running weighted average value of samples from subsequent time periods, which is provided back to the system management processor via the bus interface 218 and the system bus 110. Again, the information described above with which the sensor is programmed may be referred to as “configuration information.”
The method then proceeds to block 320, by programming a management processor with management firmware configured to analyze data collected from the plurality of sensors. For example, the system management processor 120 may be programmed with the management firmware program 125 by the external memory 190 as part of a firmware programming of the SoC 105, and the management firmware program 125 may be configured to independently analyze data from the SoC temperature sensor monitors and the SoC power event monitors, as described with respect to
The method then proceeds to block 330, by concurrently receiving data from the plurality of sensors at the management processor. For example, the system management processor 120 receives data written into the sensor data buffer 120 from the power event monitors 102a-108a, 120a, and 132a-134a in response to a triggering event from the management firmware program 125, and from the temperature sensor monitors 102b-108b, 120b, and 132b-134b independently as programmed, via the system bus 110, as described with respect to
The method then proceeds to block 340, by determining a response by the management firmware program 125 based on the concurrently-received data. For example, the management firmware program 125 may determine that one of the processing cores 102-108 should have its frequency reduced in response to data showing that a temperature sensor monitors 102a-108a associated with that processing core 102-108 is causing the SoC 105 to approach its TDP. Further, those having skill in the art will recognize that other responses are possibly, and are explicitly within the scope of the teachings of the present disclosure. In one aspect, the management firmware program 125 may determine that although an instantaneous power limit has been reached, a thermal limit has not been reached, and thus may allow the SoC 105 to temporarily exceed the instantaneous power limit, so long as an average power limit over a time period is not exceeded. In another aspect, where the system bus 110 is clocked independently of the processing cores 102-108, the memory controllers 132-134, and the system management processor 120, if the management firmware program 125 determines that all other parts of the SoC 105 are running at a maximum frequency but either an instantaneous or average power limit has not been reached, the management firmware program 125 may allow the system bus 110 to run at a higher frequency to take advantage of the power headroom.
The exemplary system-on-chip including a system management processor and management firmware program for collecting and managing data from a plurality of sensor circuits across an SoC that may according to aspects disclosed herein and discussed with reference to
In this regard,
Other master and slave devices can be connected to the system bus 410. As illustrated in
The processor SoC 401 may also be configured to access the display controller(s) 460 over the system bus 410 to control information sent to one or more displays 462. The display controller(s) 460 sends information to the display(s) 462 to be displayed via one or more video processors 461, which process the information to be displayed into a format suitable for the display(s) 462. The display(s) 462 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
