Patent Application
20080005549
Hereinafter, the preferred embodiments of the present invention will be described with reference to the drawings, in which,
The specific embodiments of the present invention are described hereinafter with reference to the drawings. It is to be noted that the embodiments are described only for illustrative purpose rather than limiting the scope of the present invention. The various numbers described here are not intended to limit the present invention, and appropriate amendments to these numbers can be made by those skilled in the art as desired.
When a computer is powered on, a CPU is in a real mode state, and a default CS (code segment register):IP (instruction pointer) points to a BIOS Flash ROM. That is, after the system is powered on, the CPU reads a first instruction from the BIOS Flash ROM, and begins to run BIOS programs (S10).
The CPU initializes a 16-bit Big-Real mode (which is a 16-bit code/32-bit address mode), where register values of a DS (data segment register), an ES (extra segment register), a FS (flag segment register), a GS (global segment register) and a SS (stack segment register) are 0. The CPU is capable of addressing a memory space of 0-4 GB. However, fetch of the CPU is still in the 16-bit CS:IP mode (S11).
The CPU turns on an NEM (No-Eviction Mode) mode of a cache, initializes a Cache-As-RAM (CAR), and designates a base address for the CAR space. Thereafter, the operations on the CAR space are based on the base address (S12).
The CPU copies the BIOS programs from the BIOS Flash ROM to the CAR space, and sets an Entry through which the BIOS programs jump to the CAR from the Flash ROM and a Return Entry through which the BIOS programs return to the Flash ROM from the CAR (S13).
The CPU switches to a 32-bit protect mode, where the CPU is completely in the 32-bit mode regardless of fetching or addressing, which is so called USE32 mode, so that the CPU may run the BIOS programs from the CAR space (S14).
The CPU jumps to the program Entry to the CAR space from the Flash ROM by an instruction of “Far Jump”. Thereafter, the CPU runs the BIOS programs completely in the CAR space (S15).
Running in the 32-bit protect mode, the CPU reads and runs the BIOS programs from the CAR space, and at the same time stores intermediate results of the running programs (S16).
At the end of running the BIOS programs in the CAR space, the CPU initializes a system memory (S17).
After the system memory is initialized, the CPU switches back to the 16-bit Big-Real mode (USE16 code/USE32 data), so as to escape from the CAR space (S18).
The CPU jumps to the Return Entry to the Flash ROM from the CAR again by the instruction of “Far Jump”, so the CPU again reads the BIOS programs from the Flash Rom (S19).
Before using the system memory, the BIOS turns off the NEM mode of the cache, turns off the Cache-As-RAM function, and restores the cache to the default state (S20).
The CPU copies the BIOS modules that have not been run yet to the system memory from the BIOS Flash ROM (S21).
The CPU runs the BIOS programs from the system memory, instead of reading the BIOS instructions from the BIOS Flash ROM, again by means of the jump instruction. The CPU runs all of the BIOS programs from the system memory so as to finish the initialization of the computer platform and finally enter an OS or Shell environment (S22).
The embodiments described above are intended to illustrate while not limit the technical solution of the present invention. Although the present invention is described referring to the above embodiments, it is to be understood by those skilled in the art that modifications and equivalent replacements to the present invention are possible, and those modifications and partial replacements without departing from the spirit and scope of the present invention all fall into the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200610090794.0 | Jun 2006 | CN | national |
