The above and other objects, features, and advantages of the present invention will become more apparent when taken in conjunction with the following description and drawings wherein identical reference numerals have been used, where possible, to designate identical features that are common to the figures, and wherein:
a shows a first cross-sectional view of a semiconductor substrate containing devices between two shallow trench isolations with sidewall implants in embodiments in accordance with the invention; and
b shows a second cross-sectional view of a semiconductor substrate containing devices between two shallow trench isolations with sidewall implants in embodiments in accordance with the invention.
The present invention includes a method for forming corner implants in STI regions of an integrated circuit. The implant is self-aligned to the STI corner without the need for additional photoresist masking or exposing the STI corner, which can lead to silicon pitting. The present invention is described with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in may different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided to fully convey the concept of the present invention to those skilled in the art. The drawings are not to scale and many portions are exaggerated for clarity.
Referring to
Etch-stop layer 21 is formed on the surface of semiconductor substrate 20. In one embodiment in accordance with the invention, etch-stop layer 21 is formed as a thin layer of silicon dioxide or polysilicon. A silicon dioxide etch-stop layer may be grown on the substrate in oxygen or steam typically at 800-1200° C. Alternatively, etch stop layer 21 may be deposited directly on the surface of semiconductor substrate 20 by oxide chemical vapor deposition. Oxide chemical vapor deposition is accomplished by a low-pressure low temperature deposition or a plasma enhanced chemical vapor deposition.
First hard mask layer 22 is deposited on etch-stop layer 21 via traditional processes such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). First hard mask layer 22 is configured as any mask layer that is deposited or grown on the device. Examples of a hard mask layer include, but are not limited to, silicon nitride, polysilicon and a metal film.
Referring to
The implant energy depends on the particular dopant used and is typically between 5-200 KeV for an implant depth typically between 100 and 500 A. The implant profile distribution is such that the implant dopant remains near the surface of substrate 20. If thermal processing occurs after implantation the dopant will diffuse away from the initial implant area. This diffusion is accounted for when choosing the initial implant depth and concentration of the elementary dopant.
Photoresist mask 23 is then removed by an oxygen ashing process, wet sulfuric acid mixed with peroxide, or solvent chemistry methods. If adequate thickness is used for first hard mask layer 22, photoresist mask 23 is removed and first hard mask layer 22 is the protective mask for the implant in an embodiment in accordance with the invention. In another embodiment in accordance with the invention, shallow implant 24 is formed in substrate 20 before first hard mask layer 22 is ansiotropically etched.
Referring to
In one embodiment in accordance with the invention, shallow trench 40 typically has a depth between 0.3 and 0.5 μm and a width between 0.15 and 0.6 μm. The width of shallow trench 40 should be as small as possible to minimize the amount of semiconductor substrate used for the STI regions. Minimizing the size of the STI regions advantageously increases the amount of substrate that is available for photodetectors in an image sensor.
Referring to
Implant dopant 28 is of the same conductivity type as the corner implants 27. In one embodiment in accordance with the invention, implant dopant 28 is also the same dopant as the shallow implant 24 dopant. Implant dopant 28 can be an n-type dopant such as phosphorus, arsenic, or antimony, or a p-type dopant such as boron, aluminum, gallium or indium.
Dielectric layer 29 is typically formed on the regions of the silicon implanted with dopant 28 by a low-pressure chemical vapor deposition, an atmospheric pressure chemical vapor deposition, a plasma enhanced chemical vapor deposition, or a high density plasma deposition. Examples of a dielectric material that can be used for dielectric layer 29 include, but are not limited to, a liner oxide or nitride. Dielectric layer 29 can be grown or deposited either prior to or after the implantation of implant dopant 28. Isolation trench 40 is then filled with a dielectric material (not shown).
Referring to
b shows a second cross-sectional view of a semiconductor substrate containing devices between two shallow trench isolations with sidewall implants in embodiments in accordance with the invention. The conductivity type of corner implants 27, implant dopant 28, photodetectors 30, 31, floating diffusion 33, well 34, and pining layers 35, 36 is reversed with respect to the conductivity types shown in
The first hard mask layer and second hard mask layer have been removed from the structure shown in
Reference is made to and priority claimed from U.S. Provisional Application Ser. No. 60/842,075, filed Sep. 1, 2006 entitled METHOD FOR ADDING AN IMPLANT AT THE SHALLOW TRENCH ISOLATION CORNER.
Number | Date | Country | |
---|---|---|---|
60842075 | Sep 2006 | US |