1. Field of the Invention
The present invention relates to a chip design, and more particularly, to a method for checking whether I/O (input/output) cells in a chip design have connection errors or not and associated computer readable medium.
2. Description of the Prior Art
In order to check whether I/O devices (i.e. I/O cells and I/O pads) in a chip design have connection errors or not, a static timing analysis (STA) or dynamic analysis is generally used to analyze the functions/operations of the whole chip. If the above analysis tool reports function failed or timing variation, a designer needs to sequentially analyze all the related timing paths to find the reason. However, the designer may waste much time to find the timing paths and to analyze the timing analysis report, and some analysis points may be missed.
It is therefore an objective of the present invention to provide a method for checking whether I/O cells in a chip design have connection errors or not, which can quickly report which nodes of I/O cells have connection errors, to solve the above-mentioned problems.
According to one embodiment of the present invention, a computer readable medium comprises a program code for checking whether an I/O cell of a chip design has a connection error or not, where the chip design comprises a plurality of I/O cells and a plurality of blocks, and when the program code is executed by a processor, the program code executes following steps: checking a connection between the I/O cell and a block by utilizing a check item corresponding to an attribute of the I/O cell to generate a checking result; and determining whether the I/O cell has a connection error according to the checking result.
According to another embodiment of the present invention, a method for checking whether an I/O cell of a chip design has a connection error or not is disclosed, where the chip design comprises a plurality of I/O cells and a plurality of blocks, and the method comprises: executing a program code to check a connection between the I/O cell and a block by utilizing a check item corresponding to an attribute of the I/O cell to generate a checking result; and determining whether the I/O cell has a connection error according to the checking result.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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In Step 200, the flow starts. Then, in Step 202, a connection between an I/O cell and a block is checked by using a check item corresponding to an attribute of the I/O cell to generate a checking result. Then, in Step 204, it is determined whether the I/O cell has a connection error according to the checking result. Finally, after checking the I/O cells in the chip design, report which I/O cell and which node of the I/O cell has connection error in a hierarchy manner.
In detail, in the chip design, each I/O cell has its own cell name, each I/O cell includes at least one node, and each node has a pin name; each block has a block name, each I/O cell includes at least one node, and each node has a pin name; and the name checks of the default I/O cell library model 124 can set that the node having a specific pin name cannot connect to a block having a specific block name. For example, please refer to
In addition, the cell name check of the default I/O cell library model 124 can set a rule that the node, having a specific pin name, of the I/O cells must be connected to a specific node of a specific block. If the rule is not satisfied, the checking result generated by the program code 122 will indicate this connection error, and the program code 122 will report that the node has the connection error.
In addition, the pin name check of the default I/O cell library model 124 can set a rule that a first node having a first pin name must be directly connected to a second node having a second pin name of a second I/O cell. For example, please refer to
In addition, when the I/O cell has a node, the block has a block node, the node of the I/O cell is directly connected to the block node, the check items may comprises an input/output direction, cell name and pin name check, and the program code 122 uses the input/output direction, cell name and pin name (i.e., node name and block node name) check to compare input/output directions of the node and the block node to generate the checking result to indicate that whether the connection is correct or not.
In addition, a node of the I/O cell of the chip design may have a current attribute, and a current attribute check of the default I/O cell library model 124 can set a rule that a node having a first current attribute must be directly connected to a node having a second current attribute. In this embodiment, the current attribute can be a specific current direction. For example, if a node of the I/O cell is an entering current of an N-type transistor (NMOS), the node of the I/O cell must be connected to a leaving current of a P-type transistor (PMOS) of another I/O cell or another block; and if a node of the I/O cell is a leaving current of a P-type transistor (PMOS), the node of the I/O cell must be connected to an entering current of an N-type transistor (NMOS) of another I/O cell or another block. If one or more nodes of the I/O cells of the chip design fail to satisfy the rule of the current attribute check of the default I/O cell library model 124, the checking result generated by the program code 122 will indicate this connection error, and the program code 122 will report that the node has the connection error.
In addition, a node of the I/O cell of the chip design may have a voltage attribute, and a voltage attribute check of the default I/O cell library model 124 can check whether an operating voltage of the node of the I/O cell is the same as an operating voltage of a node of a block including the I/O cell. If one or more nodes of the I/O cells of the chip design fail to satisfy the rule of the voltage attribute check of the default I/O cell library model 124, the checking result generated by the program code 122 will indicate this connection error, and the program code 122 will report that the node has the connection error. For example, if the operating voltage of the node of the I/O cell is 3.3V, the operating voltage of the node of the block should also be 3.3V; otherwise the program code 122 will report that the node has the connection error to prevent the node of the I/O cell operated in 3.3V from connecting to the node operated in 1.2V or other operating voltages.
In light of above, the method for checking I/O cell connections of the present invention can quickly report which nodes of I/O cells have connection errors. In addition, because the check method of the present invention is a static analysis, compared with the prior art static analysis and other dynamic analysis, the check method of the present invention does not need much manual check time, and the errors caused by manual check can be decreased.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Date | Country | Kind |
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101116169 | May 2012 | TW | national |