Claims
- 1. A method for optimizing a layout design based on a first gate-level design, comprising:
(a) obtaining a placement of circuit elements of said gate-level design; (b) based on said placement, providing routing or routing estimates between circuit elements; (c) based on said routing or routing estimates, performing a timing analysis to provide estimates of interconnect delays between circuit elements; (d) performing a logic optimization operation to obtain a second gate-level logic design based on a cost function, said cost function being a function of said estimates of interconnect delays; (e) repeating (b)-(d) until said cost function is less than a predetermined value.
- 2. A method as in claim 1, further comprising:
dividing said circuit elements into clusters; and applying (b) through (e) on the subclusters.
- 3. A method as in claim 2, wherein said dividing step and said applying step are recursively applied to said clusters until said cluster include only primitive circuit elements.
- 4. A method as in claim 2, further comprising a placement optimization operation which reassigns circuit elements in a selected cluster to a second cluster mapped to a portion of said layout design adjacent the portion of said layout design mapped to said selected cluster.
- 5. A method as in claim 1, wherein said logic optimization operation inserts or deletes buffers between circuit elements.
- 6. A method as in claim 1, wherein said logic optimization operation provides one of several logic circuits performing substantially the same logic function.
- 7. A method as in claim 2, wherein said plurality of clusters are grouped into a plurality of cluster groups and wherein each of said mapping step, said performing a timing analysis step, said performing a logic optimization operation step and said routing step is applied concurrently to each cluster group using multiple processing units.
- 8. A method as in claim 2, wherein said clusters are divided so that connectivity amongst elements within a cluster are higher than connectivity amongst elements of different clusters.
- 9. A method as in claim 1, wherein said circuit elements are provided in a logic net list.
- 10. A method as in claim 1, further providing an initialization step which includes in said layout design test structures.
- 11. A method for designing an integrated circuit, comprising:
(a) providing a register-transfer level logic design of said integrated circuit; (b) using a logic synthesis tool, synthesizing a gate-level logic design of said integrated circuit from said register-transfer level logic design of said integrated circuit; (c) using a timing model, performing a static timing analysis of said gate-level logic design; (d) placing said gate-level logic design into a first placement representing mappings of circuit elements of said gate-level logic design to physical locations of said integrated circuit, said placing step including interconnect delay-driven circuit placement and logic optimization steps; (e) extracting from said mappings of circuit elements values of timing parameters of said timing model and updating said timing model; (g) providing a physical design based on said mappings of circuit elements; (h) extracting from said physical design and resynthesizing using said logic synthesis tool a second gate-level logic circuit and updating said timing model (i) repeating (d) to (h) according to a cost function, until such cost function attains value less than a predetermined value; and (j) performing a final static timing analysis to verify that timing goals are met.
- 12. A method as in claim 11, wherein (d) comprises:
(a1) obtaining a placement of said circuit elements; (b1) based on said placement, providing routing or routing estimates for circuit elements; (c1) performing a timing analysis to provide estimates of interconnect delay between circuit elements; (d1) performing a logic optimization operation to obtain a second gate-level logic design based on a cost function, said cost function being a function of said estimates of interconnect delays; (e1) based on said second gate-level logic design, providing an improved plurality of clusters; and (f1) repeating (b1)-(e1) until said cost function is less than a predetermined value.
- 13. A method as in claim 12, further comprising:
dividing said circuit elements into a plurality of clusters; and applying (b1) through (f1) on the clusters.
- 14. A method as in claim 13, wherein said dividing step and applying step are recursively applied to said clusters until said clusters include only primitive circuit elements.
- 15. A method as in claim 13, further comprising a placement optimization operation which reassigns circuit elements in a selected cluster to a second cluster mapped to a portion of said layout design adjacent the portion of said layout design mapped to said selected cluster.
- 16. A method as in claim 12, wherein said logic optimization operation inserts or deletes buffers between circuit elements.
- 17. A method as in claim 12, wherein said logic optimization operation provides one of a plurality of logic circuits performing substantially the same logic function.
- 18. A method as in claim 13, wherein said plurality of clusters are grouped into a plurality of cluster groups and wherein each of said mapping step, said performing a timing analysis step, said performing a logic optimization operation step and routing step is applied concurrently to each cluster group using multiple processing units.
- 19. A method as in claim 13, wherein said clusters are divided so that connectivity amongst elements within a cluster are higher than connectivity amongst elements of different clusters.
- 20. A method as in claim 12, wherein said circuit elements are provided in a logic net list.
- 21. A method as in claim 12, further providing an initialization step which includes in said layout design test structures.
- 22. An integrated circuit having a layout design created by a process comprising:
(a) obtaining a placement of circuit elements of a gate-level design; (b) based on said placement, providing routing or routing estimates between circuit elements; (c) based on said routing or routing estimates, performing a timing analysis to provide estimates of interconnect delays between circuit elements; (d) performing a logic optimization operation to obtain a second gate-level logic design based on a cost function, said cost function being a function of said estimates of interconnect delays; (e) partitioning said second gate-level logic design; and (f) repeating (b)-(e) until said cost function is less than a predetermined value.
- 23. An integrated circuit as in claim 22, said layout design being created by applying further:
dividing each cluster into a plurality of clusters; and applying (b) through (f) on the clusters.
- 24. An integrated circuit as in claim 23, wherein said dividing step and applying step are recursively applied to said subclusters until said subcluster include only primitive circuit elements.
- 25. An integrated circuit as in claim 23, further comprising a placement optimization operation which reassigns circuit elements in a selected cluster to a second cluster mapped to a portion of said layout design adjacent the portion of said layout design mapped to said selected cluster.
- 26. An integrated circuit as in claim 22, wherein said logic optimization operation inserts or deletes buffers between circuit elements.
- 27. An integrated circuit as in claim 22, wherein said logic optimization operation provides one of a plurality of logic circuits performing substantially the same logic function.
- 28. An integrated circuit as in claim 23, wherein said plurality of clusters are grouped into a plurality of cluster groups and wherein each of said step mapping step, said performing a timing analysis step, said performing a logic optimization operation step and said routing step is applied concurrently to each cluster group using multiple processing units.
- 29. An integrated circuit as in claim 23, wherein said clusters are divided so that connectivity amongst elements within a cluster are higher than connectivity amongst elements of different clusters.
- 30. A computer system coupled to a shared memory accessible to a plurality of computer systems, comprising:
a central processing unit; an operation system which provides services for creating and executing multiple threads; an interface to said shared memory, said interface reading tasks from and writing tasks to a task queue residing in said shared memory, and reading from and writing to design data of an integrated circuit residing in said shared memory; a memory containing application programs for processing said design data read from said shared memory and writing back said processed design data to said shared memory through said interface; wherein said applications programs include programs for performing in a method for optimizing a layout design based on a gate-level design: (a) obtaining a placement of circuit elements of said gate-level design; (b) based on said placement, providing routing or routing estimates between circuit elements; (c) based on said routing or routing estimates, performing a timing analysis to provide estimates of interconnect delays among circuit elements; (d) performing a logic optimization operation to obtain a second gate-level logic design based on a cost function, said cost function being a function of said estimates of interconnect delays; (e) based on said second gate-level logic design, providing an improved plurality of clusters; and (f) repeating (b)-(e) until said cost function is less than a predetermined value.
- 31. A computer system as in claim 30, said method further comprising:
dividing said circuit elements into clusters; and applying (b) through (f) on the clusters.
- 32. A computer system as in claim 31, wherein said dividing step and applying step are recursively applied to said clusters until each of said clusters include only primitive circuit elements.
- 33. A method as in claim 2, wherein said logic optimization operation reassigns circuit elements in a selected cluster to a second cluster mapped to a portion of said layout design adjacent the portion of said layout design mapped to said selected cluster.
- 34. A method as in claim 13, wherein said logic optimization operation reassigns circuit elements in a selected cluster to a second cluster mapped to a portion of said layout design adjacent the portion of said layout design mapped to said selected cluster.
- 35. An integrated circuit as in claim 32, wherein said logic optimization operation reassigns circuit elements in a selected cluster to a second cluster mapped to a portion of said layout design adjacent the portion of said layout design mapped to said selected cluster
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
[0001] The present application is a continuation application of U.S. patent application Ser. No. 09/097,299, entitled “Method for Design Optimization Using Logical and Physical Information,” by Douglas B. Boyle et al., filed on Jun. 12, 1998, which is a continuation-in-part application of U.S. patent application Ser. No., 09/021,973, entitled “Performance Driven Design Optimization Using Logical and Physical Information,” by Douglas B. Boyle et al., filed Feb. 11, 1998, now U.S. Pat. No. 6,099,580, issued Aug. 8, 2000. U.S. patent application Ser. Nos. 09/097,299 and 09/021,973 are both assigned to Monterey Design Systems, Inc., which is also the Assignee of the present application.
Continuations (1)
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09097299 |
Jun 1998 |
US |
Child |
09801010 |
Mar 2001 |
US |
Continuation in Parts (1)
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09021973 |
Feb 1998 |
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09097299 |
Jun 1998 |
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