Claims
- 1. An electrical circuit inspection method, comprising:
acquiring an image representing a board pattern of a circuit board; obtaining width information relating to said board pattern; and making a defect determination for said board pattern based on an analysis of proximal width information.
- 2. The inspection method as set forth in claim 1, wherein said analysis of said proximal width information includes identification of a non vector portion of said board pattern.
- 3. The inspection method as set forth in claim 2, wherein said identifying of said non vector portion is performed using a look-up table having width indicia in separate processing channels.
- 4. The inspection method as set forth in claim 3, wherein, when said proximal width information for said defect determination is obtained from just one channel, a defect is indicated.
- 5. The inspection method as set forth in claim 4, wherein said proximal width information for said just one channel indicates a vector preceding and succeeding said non vector portion.
- 6. The inspection method as set forth in claim 2, wherein said proximal width information is obtained using a morphological process.
- 7. The inspection method as set forth in claim 6, wherein said morphological process is an erosion process.
- 8. The inspection method as set forth in claim 2, further comprising identifying an indicia pattern of said non vector portion.
- 9. The inspection method as set forth in claim 8, further comprising:
providing an indicia pattern dictionary, and characterizing said non vector portion based on a correspondence between said indicia pattern of said non vector portion and a predetermined indicia pattern in said indicia pattern dictionary.
- 10. The inspection method as set forth in claim 1, wherein said board pattern is a conductor area.
- 11. The inspection method as set forth in claim 1, wherein said board pattern is a non-conductor area.
- 12. A method for manufacturing electrical circuits, comprising:
forming at least one board pattern on a substrate; acquiring an image representing said at least one board pattern and said substrate; evaluating said image to obtain width dimension values corresponding to the width of said at least one board pattern at a multiplicity of locations; repairing a conductor or discarding a substrate at least partially in response to an indication of an aberration in the width of board patterns, said indication being obtained from analysis of proximal width information representing localized changes in board pattern width dimension values.
- 13. The manufacturing method as set forth in claim 12, wherein said analysis of said proximal width information includes identification of a non vector portion of said board pattern.
- 14. The manufacturing method as set forth in claim 13, wherein said identifying of said non vector portion is performed using a look-up table having width indicia in separate processing channels.
- 15. The manufacturing method as set forth in claim 14, wherein, when said proximal width information for said defect determination is obtained from just one channel, a defect is indicated.
- 16. The manufacturing method as set forth in claim 15, wherein said proximal width information for said just one channel indicates a vector preceding and succeeding said non vector portion.
- 17. The manufacturing method as set forth in claim 13, wherein said proximal width information is obtained using a morphological process.
- 18. The manufacturing method as set forth in claim 17, wherein said morphological process is an erosion process.
- 19. The manufacturing method as set forth in claim 13, further comprising identifying an indicia pattern of said non vector portion.
- 20. The manufacturing method as set forth in claim 19, further comprising:
providing an indicia pattern dictionary, and characterizing said non vector portion based on a correspondence between said indicia pattern of said non vector portion and a predetermined indicia pattern in said indicia pattern dictionary.
- 21. The manufacturing method as set forth in claim 12, wherein said board pattern is a conductor area.
- 22. The manufacturing method as set forth in claim 11, wherein said board pattern is a non-conductor area.
- 23. An electrical circuit inspection method, comprising:
automatically producing, in a learn mode, a reference image having non-global acceptable line width ranges; and inspecting a circuit board, in an inspect mode, using said reference image.
- 24. The inspection method as set forth in claim 23, wherein said reference image is produced by:
acquiring an image representing a board pattern of a circuit board; obtaining width information relating to said board pattern; and making a defect determination for said board pattern based on an analysis of proximal width information.
- 25. The inspection method as set forth in claim 24, wherein said image is obtained from a non-defective representation of a circuit board.
- 26. The inspection method as set forth in claim 25, wherein said non-defective representation is a CAM image.
- 27. The inspection method as set forth in claim 24, wherein said analysis of said proximal width information includes identification of a non vector portion of said board pattern.
- 28. The inspection method as set forth in claim 27, wherein said identifying of said non vector portion is performed using a look-up table having width indicia in separate processing channels.
- 29. The inspection method as set forth in claim 28, wherein, when said proximal width information for said defect determination is obtained from just one channel, a defect is indicated.
- 30. The inspection method as set forth in claim 29, wherein said proximal width information for said just one channel indicates a vector preceding and succeeding said non vector portion.
- 31. The inspection method as set forth in claim 27, wherein said proximal width information is obtained using a morphological process.
- 32. The inspection method as set forth in claim 31, wherein said morphological process is an erosion process.
- 33. The inspection method as set forth in claim 27, further comprising identifying an indicia pattern of said non vector portion.
- 34. The inspection method as set forth in claim 33, further comprising:
providing an indicia pattern dictionary, and characterizing said non vector portion based on a correspondence between said indicia pattern of said non vector portion and a predetermined indicia pattern in said indicia pattern dictionary.
- 35. The inspection method as set forth in claim 24, wherein said board pattern is a conductor area.
- 36. The inspection method as set forth in claim 24, wherein said board pattern is a non-conductor area.
- 37. The inspection method as set forth in claim 23, wherein said reference comprises:
a map of conductors; a first indication in said map of the width of a first plurality of conductors at a first multiplicity of locations; and a second indication in said map of the width of a conductor at a second location.
- 38. A method for manufacturing electrical circuits comprising:
forming a portion of electrical circuit pattern on a substrate, said electrical circuit pattern including at least one sloped conductor having a first width at a first end, a second width at a second end, and a sloping edge connecting said first end and said second end; inspecting said electrical circuit pattern; detecting the presence or absence of defects along said at least one sloped conductor; and discarding or repairing said electrical circuit pattern in response to said inspecting.
- 39. A method for inspecting electrical circuits comprising:
acquiring an image of an electrical circuit to be inspected; identifying regions corresponding to conductors and regions not corresponding to conductors; morphologically processing regions not corresponding to conductors to detect defects in conductors.
- 40. A method for inspecting electrical circuits according to claim 39 and wherein said morphologically processing regions not corresponding to conductors comprises artificially defining at least a part of said regions not corresponding to conductors as pseudo conductors.
- 41. A method for inspecting electrical circuits according to claim 39 and wherein said morphologically processing includes morphologically eroding said regions not corresponding to conductors and identifying nicks in said regions not corresponding to conductors.
- 42. A method for inspecting electrical circuits according to claim 41 and wherein said morphologically processing includes correlating nicks in said regions not corresponding to conductors to protrusions in said regions corresponding to conductors.
- 43. A method for preparing a reference for use in inspecting electrical circuits, comprising:
acquiring an image of an electrical circuit believed to be not defective; analyzing said image to detect the presence of image portions indicative of nicks in conductors; and discarding from use as a reference an image which has one or more portions that are indicative of nicks.
- 44. A method according to claim 43 and wherein said analyzing includes acquiring width data for a plurality of image portions corresponding to conductors in said electrical circuit.
- 45. A method according to claim 44 and wherein said analyzing further includes detecting width defects from evaluation of proximal width data based on the application of a rule.
- 46. A method according to claim 45 and wherein the rule is that a nick is present when a portion of conductor of relatively narrow width is located between two adjacent portions of generally uniform relatively wide width.
- 47. A method for preparing a reference for use in inspecting electrical circuits, comprising:
acquiring an image of an electrical circuit believed to be not defective; analyzing said image to detect the presence of image portions indicative of nicks in conductors; and in images having portions that are indicative of nicks, masking at least some of said portions that are indicative of nicks.
- 48. A method according to claim 47 and wherein said analyzing includes acquiring width data for a plurality of image portions corresponding to conductors in said electrical circuit.
- 49. A method according to claim 48 and wherein said analyzing further includes detecting width defects from evaluation of proximal width data based on the application of a rule.
- 50. A method according to claim 49 and wherein the rule is that a nick is present when a portion of conductor of relatively narrow width is located between two adjacent portions of generally uniform relatively wide width.
CROSS-REFERENCE TO RELATED APPLICATIONS.
[0001] This application claims the benefit of U.S. Provisional Application No. 60/237,805, filed Oct. 4, 2000. Application 60/237,805 is incorporated herein by reference in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60237805 |
Oct 2000 |
US |