Claims
- 1. A method of identifying a first circuit node shorted to a second circuit node, said first circuit node shorted to said second circuit node defining a pair of bridged circuit nodes, said method comprising the steps of:(a) establishing a composite signature dictionary having a plurality of signature entries wherein each entry in the dictionary corresponds to a pair of circuit nodes; (b) eliminating unrealistic fault signature entries within said composite signature directory in response to inductive fault analysis; and (c) comparing fault signatures for circuit nodes to said entries in said dictionary to determine a diagnostic match indicating a bridged circuit node.
- 2. A method as recited in claim 1, wherein said unrealistic fault signature entries comprise signature entries that place identical values on said pair of circuit nodes.
- 3. A method of identifying a first circuit node shorted to a second circuit node, said first circuit node shorted to said second circuit node defining a pair of bridged circuit nodes, said method comprising:(a) establishing a composite signature dictionary having a plurality of signature entries wherein each entry in the dictionary corresponds to a pair of circuit nodes; (b) identifying signature entries that place opposite logical values on the bridged nodes and that detect single stuck-at faults on both of said pair of circuit nodes within said signature dictionary as required diagnostic matches; and (c) comparing fault signatures for circuit nodes to said entries in said dictionary to determine diagnostic matches indicating a bridged circuit node.
- 4. A method as recited in claim 3, wherein all said match requirements must result in fault errors being detected during said diagnostic matching.
- 5. A method of identifying a first circuit node shorted to a second circuit node, said first circuit node shorted to said second circuit node defining a pair of bridged circuit nodes, said method comprising:(a) establishing a composite signature dictionary having a plurality of signature entries wherein each entry in the dictionary corresponds to a pair of circuit nodes; (b) ranking of said signature entries based on the quantitative measure of relative accept-or-exclude criteria for each entry; and (c) comparing fault signatures for circuit nodes to said entries in said dictionary to determine a diagnostic match indicating a bridged circuit node.
- 6. A method as recited in claim 5, wherein said relative accept-or-exclude criteria is based upon the expectation of said bridged circuit node fault occurring within each of said signature entries.
- 7. A method as recited in claim 6, further comprising:identifying signature entries that place opposite logical values on the bridged nodes and that detect single stuck-at faults on both of said pair of circuit nodes within said signature dictionary as required diagnostic matches; and wherein said relative accept-or-exclude criteria is based upon the expectation of said bridged circuit node fault occurring within said required diagnostic matches.
- 8. A method as recited in claim 6, wherein said relative accept-or-exclude criteria is based upon determining which of said entries are expected to result lower amounts of misprediction.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 08/962,711 filed on Nov. 3, 1997, now U.S. Pat. No. 6,202,181, which claims priority from U.S. application serial No. 60/030,280 filed on Nov. 4, 1996, both of which are incorporated herein by reference.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
This invention was made with Government support under Grant Nos. MIP 9158490 and MIP 915849, awarded by the National Science Foundation. The Government has certain rights in this invention.
US Referenced Citations (4)
Non-Patent Literature Citations (4)
Entry |
Lavo, David B., “Diagnosing Bridging Faults with Single Stuck-At Information”, University of California, Santa Cruz, Masters Thesis, pp. 1-56, Jun. 1996. |
Lavo et al., “Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis”, Proceedings of the IEEE 1996 International Test Conference, pp. 601-610, Oct. 1996. |
Millman, S. et al., “Diagnosing CMOS Bridging Faults with Stuck-At Fault Dictionaries”, Proceedings of the IEEE 1990 International Test Conference, pp. 860-870, Sep. 1990. |
Chess et al., “Diagnosis of Realistic Bridging Faults with Single Stuck-At Information”, Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pp. 185-192, Nov. 5, 1995. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/030280 |
Nov 1996 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
08/962711 |
Nov 1997 |
US |
Child |
09/758303 |
|
US |