METHOD FOR ERASING NON-VOLATILE MEMORY

Abstract

A method for erasing a non-volatile memory is provided. The non-volatile memory includes a first conductive type substrate, a second conductive type well disposed in the first conductive type substrate, a first conductive type well disposed on the second conductive type well, and a memory cell disposed on the first conductive type substrate. The memory cell includes a charge trapping layer and a gate. The erasing method includes the following steps. A first voltage is applied to the gate, a second voltage is applied to the first conductive type substrate, and the second conductive type well is floating. The second voltage is large enough to induce a substrate hot hole effect. The holes are injected into the charge trapping layer by applying the first voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1A is a structural view of a conventional SONOS memory.

FIG. 1B shows a schematic view of the relation between the threshold voltage and the erasing time under different voltage differences between the gate and the substrate in a method for erasing a conventional SONOS memory.

FIG. 2A is a schematic sectional view of an embodiment according to the method for erasing a non-volatile memory of the present invention.

FIG. 2B is a simplified circuit diagram of FIG. 2A.

FIG. 3A is a schematic sectional view of another embodiment according to the method for erasing the non-volatile memory of the present invention.

FIG. 3B is a simplified circuit diagram of FIG. 3A.

FIG. 4A is a schematic sectional view of yet another embodiment according to the method for erasing a non-volatile memory of the present invention.

FIG. 4B is a simplified circuit diagram of FIG. 4A.

FIG. 5A shows a schematic view of the relation between the read current and the accumulative proportion of the non-volatile memory.

FIG. 5B shows a schematic view of the relation between the threshold voltage and the count value of the non-volatile memory.

FIG. 6 is a structural sectional view of a NAND-type non-volatile memory.

Claims

1. A method for erasing a non-volatile memory, wherein the non-volatile memory includes a first conductive type substrate, a second conductive type well disposed in the first conductive type substrate, a first conductive type well disposed on the second conductive type well, and a memory cell comprising a charge trapping layer and a gate disposed on the first conductive type substrate, the method comprising: applying a first voltage to the gate, applying a second voltage to the first conductive type substrate, and floating the second conductive type well, wherein the second voltage is large enough to induce substrate hot hole effect, and holes are injected into the charge trapping layer by applying the first voltage.

2. The method of claim 1, wherein the first voltage is larger than or equal to 20 volts, and the second voltage is −7 volts.

3. The method of claim 1, wherein the non-volatile memory has a NAND-type array structure.

4. The method of claim 1, wherein the first conductive type is N-type, and the second conductive type is P-type.

5. The method of claim 1, wherein the first conductive type is P-type, and the second conductive type is N-type.

6. The method of claim 1, wherein the material of the charge trapping layer comprises silicon nitride.

7. A method for erasing a non-volatile memory, wherein the non-volatile memory includes a first conductive type substrate, a second conductive type well disposed in the first conductive type substrate, a first conductive type well disposed on the second conductive type well, and a memory cell comprising a charge trapping layer and a gate disposed on the first conductive type substrate, the method comprising: applying a first voltage to the gate, and applying a second voltage to the first conductive type substrate, wherein the second conductive type well and the first conductive type well constitute a Zener diode, the second voltage is large enough to breakdown the Zener diode and induce substrate hot hole effect, and holes are injected into the charge trapping layer by applying the first voltage.

8. The method of claim 7, wherein the first voltage is 5 volts, and the second voltage is −7 volts.

9. The method of claim 7, wherein the non-volatile memory has a NAND-type array structure.

10. The method of claim 7, wherein the first conductive type is N-type, and the second conductive type is P-type.

11. The method of claim 7, wherein the first conductive type is P-type, and the second conductive type is N-type.

12. The method of claim 7, wherein the material of the charge trapping layer comprises silicon nitride.

13. A method for erasing a non-volatile memory, wherein the non-volatile memory includes a first conductive type substrate, a second conductive type well disposed in the first conductive type substrate, a first conductive type well disposed on the second conductive type well, and a memory cell comprising a charge trapping layer and a gate disposed on the first conductive type substrate, comprising: applying a first voltage to the gate, applying a second voltage to the first conductive type substrate, and applying a third voltage to the second conductive type well, wherein the first conductive type substrate, the second conductive type well, and the first conductive type well constitute a bipolar transistor, the third voltage is large enough to turn on the bipolar transistor, the second voltage is large enough to induce substrate hot hole effect, and holes are injected into the charge trapping layer by applying the first voltage.

14. The method of claim 13, wherein the first voltage is 5 volts, the second voltage is −7 volts, and the third voltage is 1 volt.

15. The method of claim 13, wherein the non-volatile memory has a NAND-type array structure.

16. The method of claim 13, wherein the first conductive type is N-type, and the second conductive type is P-type.

17. The method of claim 13, wherein the first conductive type is P-type, and the second conductive type is N-type.

18. The method of claim 13, wherein the material of the charge trapping layer comprises silicon nitride.