Method for estimating stress of electronic component

Abstract

A method for estimating stress of an electronic component. An electronic component including first and second elements and conductive bumps is provided. Each conductive bump has two surfaces connected to the first and second elements respectively. Two adjacent conductive bumps have a pitch therebetween. The conductive bumps includes a first conductive bump and second conductive bumps. A stress value of the first conductive bump related to a testing parameter is calculated. A stress value of each second conductive bump related to the testing parameter is calculated according to a first calculating formula. The first calculating formula is

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Chinese application serial no. 201510356926.9, filed on Jun. 25, 2015. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Field of the Invention

The invention is directed to a method for estimating stress of an electronic component and more particularly, to a method for estimating propagating stress of an electronic component.

Description of Related Art

In a semiconductor packaging process, a chip is commonly disposed on a substrate, and conductive bumps (e.g., solder balls) are often used as a bonding medium for the chip and the substrate. Although the bonding method using the conductive bumps has low cost and is easy for manufacturing, coefficients of thermal expansion (CTEs) of bonding surfaces are different. Fatigue effect resulted from repetitive changes in temperature or voltage during system operation is mainly the reason for damage to bonding points of the chip. Fatigue failure may be classified into mechanical fatigue failure and thermal fatigue failure. Mechanical fatigue failure is due to continuous transformation and movement, resulting in a decrease in mechanical strength. Thermal fatigue failure, on the other hand, is caused by poor match of coefficients of thermal expansion between two surfaces, resulting in the two surfaces pulling each other because of minor transformation generated at high and low temperatures, which, under long term influences, may easily cause the surfaces to peel off. As such, both the chip and the substrate under the chip would be damaged, which leads to the reduction in effectiveness and reliability of the chip package structure.

Accordingly, a stress generated to each conductive bump under a certain temperature or voltage variation condition in the semiconductor package is commonly calculated by utilizing finite element simulation at present, so as to estimate a lifetime of each conductive bump. However, the finite element simulation has a complicated calculation process and consumes much computing time. Therefore, how to rapidly estimate the stress and lifetime of each conductive bump in the semiconductor package has become an important subject in the art.

SUMMARY

The invention provides a method for estimating stress of an electronic component, which can facilitate in rapidly estimating the propagating stress of conductive bumps of the electronic component.

A method for estimating stress of an electronic component provided by the invention include the following steps. An electronic component including a first element, a second element and a plurality of conductive bumps is provided. Each of the conductive bumps has two opposite surfaces, and the two surfaces are respectively connected to the first element and the second element, adjacent two of the conductive bumps have a pitch therebetween, and the conductive bumps include a first conductive bump and a plurality of second conductive bumps. A stress value of the first conductive bump related to a testing parameter is calculated. A stress value of each of the second conductive bumps related to the testing parameter is calculated according to a first calculating formula. The first calculating formula is

${\sigma }_2=\frac{L}{D-2r}{\sigma }_1,$ σ₂ is the stress value of each of the second conductive bumps, L is a beeline distance between each of the second conductive bumps and the first conductive bump, D is an average of the pitches of the conductive bumps, r is a radius of each of the surfaces, and σ₁ is the stress value of the first conductive bump.

To sum up, in the method for estimating stress of the invention, an estimating concept according to the first calculating formula,

${\sigma }_2=\frac{L}{D-2r}{\sigma }_1,$ lies in that the stresses received by the conductive bumps gradually propagate toward and are accumulated at the surrounding second conductive bumps from the first conductive bump as the center. Therefore, the second conductive bump with the greater distance from the first conductive bump has the greater accumulated propagating stress. Based on this concept, in the invention, the stress value σ₁ of a single conductive bump (i.e., the first conductive bump) in the electronic component is first calculated according to the set testing parameter, and the stress value σ₁ is then substituted to the first calculating formula, so as to calculate the stress value σ₂ of each of the other conductive bumps (i.e., the second conductive bumps) related to the testing parameter. Thereby, the stress values of all the conductive bumps can be calculated rapidly to effectively estimate the lifetime of the electronic component, without utilizing finite element simulation, which has a complicated calculation process and consumes much computing time.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a top view illustrating an electronic component according to an embodiment of the invention.

FIG. 2 is a cross-sectional view of the electronic component depicted in FIG. 1 along a line I-I.

FIG. 3 is a flowchart illustrating a method for estimating stress of an electronic component according to an embodiment of the invention.

FIG. 4 illustrating testing conditions of FIG. 3.

FIG. 5 illustrates the creep rate of each second conductive bump depicted in FIG. 1 varies with time.

FIG. 6 is a partially cross-sectional view illustrating an electronic component according to another embodiment of the invention.

DESCRIPTION OF EMBODIMENTS

Referring to FIG. 1 through FIG. 3, a method for estimating stress of an electronic component of the present embodiment includes the following steps. First, an electronic component 100 as illustrated in FIG. 1 and FIG. 2 is provided. The electronic component 100 includes a first element 110, a second element 120 and a plurality of conductive bumps 130. Each of the conductive bumps 130 has two opposite surfaces S, and the two surfaces S are connected to and contact the first element 110 and the second element 120, respectively. A radius of each surface is r. Each of the conductive bumps 130 and another conductive bump 130 adjacent thereto have a pitch therebetween, and an average of the pitches of the conductive bumps 130 is D (step S602).

In the present embodiment, the electronic component 100 has, for example, a semiconductor structure, and the first element 110 and the second element 120 are, for example, a substrate and a chip in the semiconductor structure respectively, but the invention is not limited thereto. Additionally, in the present embodiment, the conductive bumps 130 are arranged equidistantly, for example, such that the pitch values of all the conductive bumps 130 are D, but the invention is not limited thereto. In other embodiments, the conductive bumps 130 may be irregularly arranged, have pitches with various sizes, and an average of the pitches is D.

In order to describe the method for estimating stress of the present embodiment conveniently, the conductive bumps 130 is divided into a central first conductive bump 132 and a plurality of second conductive bumps 134 surrounding the first conductive bump 132. Namely, the conductive bumps 130 include a first conductive bump 132 and a plurality of second conductive bumps 134. The first conductive bump 132 is located in, a geometric center of the electronic component 100, and the second conductive bumps 134 are distributed between the first conductive bump 132 and a peripheral edge of the electronic component 100. The peripheral edge is, for example, a peripheral edge 110a of the first element 110 or a peripheral edge 120a of the second element 120.

Then, a stress value of the first conductive bump 132 related to a testing parameter σ₁ is calculated (step S604). The testing parameter is a parameter set for applying a temperature cycle variation, a voltage cycling test or other types of testing conditions to the electronic component 100, for example, which is not limited in the invention. Namely, the testing parameter may be a temperature variation, a voltage variation or a variation of other testing values. Thereafter, a stress value σ₂ of each second conductive bump 134 related to the testing parameter is calculated based on the calculated stress value σ₁ of the first conductive bump 132 according to a first calculating formula. The first calculating formula is

${\sigma }_2=\frac{L}{D-2r}{\sigma }_1,$ where σ₂ is the stress value of each second conductive bump 134, L is a beeline distance between each second conductive bump 134 and the first conductive bump 132, D is the average of the pitches of the conductive bumps 130, r is the radius of each surface, and σ₁ if the stress value of the first conductive bump 132 (step S606).

An estimating concept according to the first calculating formula lies in that the stresses received by the conductive bumps 130 may gradually propagate toward and be accumulated at the surrounding second conductive bumps 134 from the first conductive bump 132 as the center. Thus, the second conductive bump 134 with the greater distance from the first conductive bump 132 has the greater accumulated propagating stress. Based on this concept, in the present embodiment, the stress value σ₁ of a single conductive bump 130 (i.e., the first conductive bump 132) in the electronic component 100 is first calculated according to the set testing parameter, and the stress value σ₁ is then substituted to the first calculating formula, so as to calculate the stress value σ₂ of each of the other conductive bumps 130 (i.e., the second conductive bumps 134) related to the testing parameter. Thereby, the stress values of all the conductive bumps 130 can be calculated rapidly to effectively estimate the lifetime of the electronic component 100, without utilizing finite element simulation, which has a complicated calculation process and consumes much computing time.

In step S604 illustrated in FIG. 3, the stress value σ₁ of the first conductive bump 132 related to the testing parameter is calculated according to a second calculating formula. The second calculating formula is

${\sigma }_1=\frac{E_{\mathrm{solder}}\left(D-2r\right)\mathrm{\Delta \alpha \Delta }T}{4\left(1+{\in }_{\mathrm{solder}}\right)h},$ where E_solder is a Young's modulus of each conductive bump 130, ∈_solder is a Poisson ratio of each conductive bump 130, Δα is a difference between a coefficient of thermal expansion (CTE) of the first element 110 and a CTE of the second element 120, h is a distance between the first element and the second element. In addition, ΔT is a testing parameter set for applying a temperature cycle variation, a voltage cycling test or other types of testing conditions to the electronic component 100. An embodiment is provided below as an example and will be described with reference to FIG. 4 hereinafter.

Referring to FIG. 4, the testing condition of the present embodiment is to apply a temperature cycle variation to the electronic component 100, and ΔT is a parameter set according to the temperature cycle variation. A period of the temperature cycle variation is, for example, 60 minutes, and a maximum and a minimum temperatures are respectively 125 and 140° C., for example. In other embodiments, the temperature cycle variation may be set to have other suitable periods, other suitable temperature variations and temperature values, which is not limited in the invention. In addition, the testing condition may also be changed to apply a voltage cycling test or other types of testing conditions to the electronic component 100, so as to set the testing parameter, which is not limited in the invention.

The estimating concept according to the first calculating formula in step S606 depicted in FIG. 3 will be described in detail hereinafter. For descriptive convenience, a coordinated position of the first conductive bump 132 at the intersection of the X and the Y axes in FIG. 1 and the stress value σ₁ are respectively defined as (0, 0) and σ_(0,0), while a coordinate position of each second conductive bump 134 and the stress value σ₂ in the two dimensional (2D) coordinate system formed by the X and the Y axes are respectively defined as (i, j) and σ_(i,j), where the stress value σ₂ of each second conductive bump 134 on the X axis is σ_(i,0), and the stress value σ₂ of each second conductive bump 134 on the Y axis is σ_(0,j). A greater absolute value of i or j represents a greater distance between the corresponding second conductive bump 134 and the first conductive bump 132. Accordingly, the stresses received by the conductive bumps 130 gradually propagate toward and are accumulated at the surrounding second conductive bumps 134 from the first conductive bump 132 as the center, such that the second conductive bump 134 with the greater distance from the first conductive bump 132 has the greater accumulated propagating stress. Thus, based on this propagating concept, σ_(i,0) is approximated to N₁σ_(0,0), σ_(0,j) is approximated to N₂σ_(0,0), a geometry relation of σ_(i,j) is √{square root over (σ_(i,0)²+σ_(0,j)³)}, where N₁ and N₂ are respectively equal to

$\frac{\Delta x}{D-2r}\mathrm{and}\frac{\Delta y}{D-2r},$ Δx is a distance from the corresponding second conductive bump 134 to the first conductive bump 132 on the X axis, and Δy is a distance from the corresponding second conductive bump 134 to the first conductive bump 132 on the Y axis. A calculating formula,

${\sigma }_{\left(i,j\right)}=\frac{\sqrt{\Delta x^2+\Delta y^2}}{D-2r}{\sigma }_{\left(0,0\right)},$ equivalent to the first calculating formula,

${\sigma }_2=\frac{L}{D-2r}{\sigma }_1,$ used in step S606 illustrated in FIG. 3 may be obtained by deriving according to the aforementioned approximation manner.

In the present embodiment, a lifetime of each second conductive bump 134 may be further estimated according to the stress value σ₂ of each second conductive bump 134, of which is specific method is described as follows. A creep rate of each second conductive bump is calculated based on the stress value σ₂ of each second conductive bump 134 according to a third calculating formula. The third calculating formula is ε≅∫{dot over (ε)}_total+δ{dot over (ε)}_transndt, where ε is the creep rate of each second conductive bump,

${\stackrel{.}{\varepsilon }}_{\mathrm{total}}=\frac{D_{L0}}{d^2}\left(e^{-\frac{Q_{\mathrm{NH}}}{\mathrm{kT}\left(t\right)}}+\frac{D_{G0}\delta }{D_{L0}d}{e}^{-\frac{Q_C}{\mathrm{kT}\left(t\right)}}\right)\exp \left(-\frac{Q_f}{\mathrm{kT}\left(t\right)}\right)\sinh \left(\frac{{\sigma }_2\Omega }{\mathrm{kT}\left(t\right)}\right),\delta {\stackrel{.}{\varepsilon }}_{\mathrm{trasn}}=\frac{1}{\eta }\left\{\stackrel{.}{\varepsilon }\left(t^{\prime }+\eta P\right)-\stackrel{.}{\varepsilon }\left(t^{\prime }\right)\right\},$ D_L0 is a lattice diffusion coefficient, d is a grain size, Q_NH is a Nabarro-Herring type vacancy migration energy, D_G0 is a grain boundary diffusion coefficient, δ is an effective width of a grain boundary, Q_C is a Coble type vacancy migration energy, Q_f is a vacancy formation energy, k is a Boltzmann's constant, Ω is an atomic volume, P is a number of testing cycles, η is a parameter of testing cycle percentage, and T(t) and {dot over (ε)}(t′) are testing functions. T(t) and {dot over (ε)}(t′) are, for example, functions corresponding to the testing condition illustrated in FIG. 4, where a single period of the temperature cycle function illustrated in FIG. 4 is 60 minutes which is divided into four temperature condition zones of 15 minutes. Namely, a time length of one temperature condition zone is 0.25 times a time length of the single period, and accordingly, the parameter of testing cycle percentage, η, is defined as 0.25.

FIG. 5 illustrates the creep rate of each second conductive bump depicted in FIG. 1 varies with time. According to the third calculating formula, a creep rate ε of each second conductive bump 134 at each time point may be calculated, as illustrated in FIG. 5, for example, and the lifetime of each second conductive bump 134 may be accordingly estimated. For example, the creep rate ε of each second conductive bump 134 will be considered as invalid if rising up to 50%, and thus, the lifetime of each second conductive bump 134 may be estimated as corresponding LT.

A table of comparing the lifetime of each conductive bump which is estimated according to the aforementioned manner with actually experiment results is provided below. Therein, the estimation and the experiment are performed, for example, under a testing condition that E_solder is 22 Gpa, ε_solder is 0.35, D is 1 mm, h is 0.12 mm, Δα is 17.6 ppm/° C. with reference to the testing conditions illustrated in FIG. 4, and the estimated and experimented results of the second conductive bumps 134 having coordinates of (2, 2), (4, 3), (6, 5) as illustrated in FIG. 1 are compared.

Coordinate	Estimated lifetime (HR)	Experimented lifetime (HR)
(2, 2)	438	450
(4, 3)	206	200
(6, 5)	93	95

According to the comparison table, the lifetime of each conductive bump which is estimated according to the aforementioned manner has not much difference from the actual experimented results and is in line with expectations.

FIG. 6 is a partially cross-sectional view illustrating an electronic component according to another embodiment of the invention. An electronic component 100′ illustrated in FIG. 6 is different from the electronic component 100 illustrated in FIG. 2 in the electronic component 100′ further including a molding compound 140. The molding compound 140 is disposed between the first element 110 and the second element 120 and covers the conductive bumps 130. Based on the disposition difference, the stress value σ₂ of each second conductive bump 134 related to the testing parameter is calculated according to a fourth calculating formula in replacement with the first calculating formula. The fourth calculating formula is

${\sigma }_2=\frac{L}{D-2r}\left({\sigma }_1-\left(E_{\mathrm{solder}}{\alpha }_{\mathrm{solder}}+E_{\mathrm{underfill}}{\alpha }_{\mathrm{underfill}}\right)\Delta T\right),$ E_underfill is a Young's modulus of the molding compound, α_underfill is a CTE of the molding compound, and D, r, L, E_solder, α_solder and ΔT are defined as above.

To summarize, in the method for estimating stress of the invention, the estimating concept according to the first calculating formula,

${\sigma }_2=\frac{L}{D-2r}{\sigma }_1,$ lies in that the stresses received by the conductive bumps gradually propagate toward and are accumulated at the surrounding second conductive bumps from the first conductive bump as the center. Therefore, the second conductive bump with the greater distance from the first conductive bump has the greater accumulated propagating stress. Based on this concept, in the invention, the stress value of a single conductive bump (i.e., the first conductive bump) in the electronic component is first calculated according to the set testing parameter, and the stress value σ₁ is then substituted to the first calculating formula, so as to calculate the stress value σ₂ of each of the other conductive bumps (i.e., the second conductive bumps) related to the testing parameter. Thereby, the stress values of all the conductive bumps can be calculated rapidly to effectively estimate the lifetime of the electronic component, without utilizing finite element simulation, which has a complicated calculation process and consumes much computing time.

Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.

Claims

1. A testing method for an electronic component within a semiconductor package, the method comprising: providing an electronic component comprising a first element, a second element and a plurality of conductive bumps, wherein each of the conductive bumps has two opposite surfaces, the two surfaces are respectively connected to the first element and the second element, a pitch is between adjacent two of the conductive bumps, and the conductive bumps comprises a first conductive bump and a plurality of second conductive bumps;applying a testing parameter associated with a testing condition variation to the electronic component to obtain a testing result;calculating a stress value of the first conductive bump based on the testing result;calculating a stress value of each of the second conductive bumps by a processor, wherein the processor uses a first calculating formula to calculate the stress value of each of the second conductive bumps related to the testing parameter, the first calculating formula is

2. The method according to claim 1, wherein the first conductive bump is located in a geometric center of the electronic component.

3. The method according to claim 1, wherein the testing parameter is a temperature variation or a voltage variation.

4. The method according to claim 1, wherein the step of calculating the stress value of the first conductive bump related to the testing parameter comprises: calculating the stress value of the first conductive bump related to the testing parameter according to a second calculating formula, wherein the second calculating formula is

5. A testing method for testing an electronic component within a semiconductor package, the method comprising: providing an electronic component comprising a first element, a second element, a plurality of conductive bumps, and a molding compound, wherein the molding compound is disposed between the first element and the second element and covers the conductive bumps, each of the conductive bumps has two opposite surfaces, the two surfaces are respectively connected to the first element and the second element, a pitch is between adjacent two of the conductive bumps, and the conductive bumps comprises a first conductive bump and a plurality of second conductive bumps;applying a testing parameter associated with a testing condition variation to the electronic component to obtain a testing result;calculating a stress value of the first conductive bump based on the testing result;calculating a stress value of each of the second conductive bumps by a processor, wherein the processor uses a fourth calculating formula to calculate the stress value of each of the second conductive bumps related to the testing parameter, the fourth calculating formula is